2016
DOI: 10.1007/978-3-319-28854-3_5
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Image Feature Extraction Acceleration

Abstract: Image feature extraction is instrumental for most of the best-performing algorithms in computer vision. However, it is also expensive in terms of computational and memory resources for embedded systems due to the need of dealing with individual pixels at the earliest processing levels. In this regard, conventional system architectures do not take advantage of potential exploitation of parallelism and distributed memory from the very beginning of the processing chain. Raw pixel values provided by the front-end … Show more

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Cited by 1 publication
(2 citation statements)
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References 34 publications
(31 reference statements)
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“…To increase the power-efficiency of camera-based architectures, focal plane processing have been investigated [10]. According to this approach, pixel-wise mixed-signal processing circuits are integrated on the sensor die to enable a first stage of processing acceleration in a distributed and efficient way [20]- [22].…”
Section: Related Workmentioning
confidence: 99%
See 1 more Smart Citation
“…To increase the power-efficiency of camera-based architectures, focal plane processing have been investigated [10]. According to this approach, pixel-wise mixed-signal processing circuits are integrated on the sensor die to enable a first stage of processing acceleration in a distributed and efficient way [20]- [22].…”
Section: Related Workmentioning
confidence: 99%
“…Typically, such devices feature a power consumption of hundreds of mW, because of the high computational and bandwidth requirements [6], [8], [9]. Power-optimized solutions rely on vision chips that integrate focal-plane processing circuits, which enable a first stage of visual processing in a distributed and efficient way at the sensor-level [10]. To extract digital signatures from the visual signal, sensor data are then transferred to the digital processing unit for post-processing operation.…”
Section: Introductionmentioning
confidence: 99%