This paper presents a high-level synthesis tool for 61 modulators (61 s) that combines an accurate SIMULINK-based time-domain behavioral simulator with a statistical optimization core. Three different circuit techniques for the modulator implementation are considered: switched-capacitor, switched-current and continuous-time. The behavioral models of these circuits, that take into account the most critical limiting factors, have been incorporated into the SIMULINK environment by using S-function blocks, which drastically increase the computational efficiency. The precision of these models has been validated by electrical simulations using HSPICE and experimental measurements from several silicon prototypes. The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for 61 synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, processing capabilities, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of 61 s using both discrete-time and continuous-time circuit techniques.

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This letter presents a new cascade ΣΔ modulator architecture with unity signal transfer function that avoids the need of digital filtering in the error cancellation logic. The combination of these two aspects make it highly tolerant to noise leakages, very robust to non-linearities of the circuitry and especially suited for low-voltage implementations at low oversampling. Behavioral simulations are presented that demonstrate the higher efficiency of the proposed topology compared to existing cascades intended for wideband applications. Introduction: Many new communication systems have arisen in recent years that demand for high-bandwidth ΣΔ modulators (ΣΔMs) in low-voltage technologies [1]-[3]. Since oversampling must be restricted to low values in wideband applications, a usual design choice in order to achieve the required performance is to employ multi-stage noise shaping (MASH) architectures with multi-bit quantization. These ΣΔ topologies circumvent the stability problems of high-order loops, but are sensitive to quantization noise leakages caused by mismatches between the analog and digital signal processing in the ΣΔ cascade [4]. An alternative ΣΔM architecture that reduces the sensitivity to noise leakages of traditional cascade ΣΔMs is the so-called Sturdy MASH (SMASH) modulator, recently presented in [1].

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This paper describes a 0.35-m CMOS chopper-stabilized switched-capacitor 2-1 cascade 61 modulator for automotive sensor interfaces. The modulator architecture has been selected from an exhaustive comparison among multiple topologies in terms of resolution, speed and power dissipation. To obtain a better fitting with the characteristics of different sensor outputs, the circuit can be digitally programmed to yield four input-to-output gain values (0 5 1 2, and 4) and has been designed to operate within the stringent environmental conditions of automotive electronics (temperature range of 40 C to 175 C). In order to relax the amplifier's dynamic requirements for the different modulator input-to-output gains, switchable capacitor arrays are used for all the capacitors in the first integrator. The design of the building blocks is based on a top-down CAD methodology which combines simulation and statistical optimization at different levels of the modulator hierarchy. The circuit is clocked at 5.12 MHz and the overall power consumption is 14.7 mW from a single 3.3-V supply and occupies 5.7 mm 2 silicon area. Experimental results show a maximum SNR of 87.3 dB within a 20-kHz signal bandwidth and 90.7 dB for 10-kHz signals, and an overall DR of 110 and 113.8 dB, respectively. These performance features place the reported circuit at the cutting edge of state-of-the-art high-resolution 61 modulators.

This paper describes a tool that combines an accurate SIMULINK-based time-domain behavioural simulator with a statistical optimizer for the automated high-level synthesis of Modulators ( Ms). The combination of high accuracy, short CPU time and interoperability of different circuit models together with the efficiency of the optimization engine makes the proposed tool an advantageous alternative for M synthesis. The implementation on the well-known MATLAB/SIMULINK platform brings numerous advantages in terms of data manipulation, flexibility and simulation with other electronic subsystems. Moreover, this is the first tool dealing with the synthesis of Ms using both Discrete-Time (DT) and Continuous-Time (CT) circuit techniques (*) .