Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this article, we propose a novel hybrid memristor-CMOS PUF circuit and demonstrate its suitability through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially less hardware overhead than previously proposed memristor-based PUF circuits while being inherently resistant to machine learningbased modeling attacks because of challenge-dependent delays of the memristor stages. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security.
Aims and ScopeThe book series Earth Systems Data and Models publishes state-of-the-art research and technologies aimed at understanding processes and interactions in the earth system. A special emphasis is given to theory, methods, and tools used in earth, planetary and environmental sciences for: modeling, observation and analysis; data generation, assimilation and visualization; forecasting and simulation; and optimization. Topics in the series include but are not limited to: numerical, datadriven and agent-based modeling of the earth system; uncertainty analysis of models; geodynamic simulations, climate change, weather forecasting, hydroinformatics, and complex ecological models; model evaluation for decision-making processes and other earth science applications; and remote sensing and GIS technology.The series publishes monographs, edited volumes and selected conference proceedings addressing an interdisciplinary audience, which not only includes geologists, hydrologists, meteorologists, chemists, biologists and ecologists but also physicists, engineers and applied mathematicians, as well as policy makers who use model outputs as the basis of decision-making processes.More information about this series at
Montgomery Algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2 ) for efficient implementation of Montgomery Multiplication (MM) Algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2 1), where = is the word size and is the digit size. No digit serial systolic architecture based on MM algorithm over GF(2 ) is reported before. The architecture is also compared to two well known digit serial systolic architectures.
Abstract. We consider a quantum polynomial-time algorithm which solves the discrete logarithm problem for points on elliptic curves over GF (2 m ). We improve over earlier algorithms by constructing an efficient circuit for multiplying elements of binary finite fields and by representing elliptic curve points using a technique based on projective coordinates. The depth of our proposed implementation is O(m 2 ), which is an improvement over the previous bound of O(m 3 ).
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