The design of a silicon Strong Physical Unclonable Function (PUF) that is lightweight and stable, and which possesses a rigorous security argument, has been a fundamental problem in PUF research since its very beginnings in 2002. Various effective PUF modeling attacks, for example at CCS 2010 and CHES 2015, have shown that currently, no existing silicon PUF design can meet these requirements. In this paper, we introduce the novel Interpose PUF (iPUF) design, and rigorously prove its security against all known machine learning (ML) attacks, including any currently known reliability-based strategies that exploit the stability of single CRPs (we are the first to provide a detailed analysis of when the reliability based CMA-ES attack is successful and when it is not applicable). Furthermore, we provide simulations and confirm these in experiments with FPGA implementations of the iPUF, demonstrating its practicality. Our new iPUF architecture so solves the currently open problem of constructing practical, silicon Strong PUFs that are secure against state-of-the-art ML attacks.
Memristor is an exciting new addition to the repertoire of fundamental circuit elements. Alternatives to many security protocols originally employing traditional mathematical cryptography involve novel hardware security primitives, such as Physically Unclonable Functions (PUFs). In this article, we propose a novel hybrid memristor-CMOS PUF circuit and demonstrate its suitability through extensive simulations of environmental and process variation effects. The proposed PUF circuit has substantially less hardware overhead than previously proposed memristor-based PUF circuits while being inherently resistant to machine learningbased modeling attacks because of challenge-dependent delays of the memristor stages. The proposed PUF can be conveniently used in many security applications and protocols based on hardware-intrinsic security.
Physically Unclonable Function (PUF) designs proposed in the recent literature vary widely in diverse characteristics such as hardware resource requirement, reliability, entropy, and robustness against mathematical cloning. Most of the standalone PUF designs suffer from either poor performance pro¿le or unacceptable resource-overhead. We present a novel PUF design paradigm, termed as PUF Composition, that utilizes smaller PUFs as design building blocks to de¿ne a "Composite PUF" having larger challenge-space and superior performance pro¿le at reasonable resource-overhead. A formal framework for PUF composition based on a probabilistic model has also been developed to enable the Composite PUF designer to have a-priori estimate of the relative qualities of several composite PUF options, without actually implementing them physically. The notion of PUF composition, and the probabilistic model developed for delay-PUFs, have both been validated using Ring Oscillator PUF (ROPUF) and Arbiter PUF (APUF) on Xilinx Spartan-3 Field Programmable Gate Array (FPGA).
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