2015
DOI: 10.1016/j.vlsi.2015.05.005
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A novel memristor based physically unclonable function

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Cited by 18 publications
(32 citation statements)
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“…when both of the inputs are at logic 1. In contrast, the technique of [7] cannot ensure output voltage any less than 0.2V when both of its output transistors saturates. This larger voltage can be a critical factor, especially when driving very small technology nodes (Section II).…”
Section: T-4m Hybrid Cmos-memristive Logic Architecturementioning
confidence: 97%
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“…when both of the inputs are at logic 1. In contrast, the technique of [7] cannot ensure output voltage any less than 0.2V when both of its output transistors saturates. This larger voltage can be a critical factor, especially when driving very small technology nodes (Section II).…”
Section: T-4m Hybrid Cmos-memristive Logic Architecturementioning
confidence: 97%
“…Based on the MRL OR gate ( Fig. 4(a)), the technique of [7] proposed a hybrid memristive XOR architecture as shown in Fig. 3(b).…”
Section: B Existing Memristive Logic Architecturementioning
confidence: 99%
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