Memristor based Random Number Generator: Architectures and Evaluation

Kumar, Vikash; Tripathy, Somanath; Mathew, Jimson

doi:10.1016/j.procs.2017.12.074

Cited by 29 publications

(26 citation statements)

References 7 publications

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“…The weaknesses of the thermal noise-based designs are its sensitivity to noise-based attacks, compromising the randomness of the output, as well as issues with the design complexity required for post-processing and tuning of the system 10,[23][24][25][26] . Many other entropy sources have been used for TRNGs, such as the timing of time dependent dielectric breakdown (TDDB) 27 , Photonics [28][29][30][31] , and current variation or switching time of emerging technologies such as ReRAM [32][33][34] . TDDB-based designs suffer from high complexity of circuit design and processing circuits which limit their use in low-area, low-power applications.…”

mentioning

confidence: 99%

Random-telegraph-noise-enabled true random number generator for hardware security

Brown

Zhang

Zhou

et al. 2020

Sci Rep

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The future security of Internet of Things is a key concern in the cyber-security field. One of the key issues is the ability to generate random numbers with strict power and area constrains. “True Random Number Generators” have been presented as a potential solution to this problem but improvements in output bit rate, power consumption, and design complexity must be made. In this work we present a novel and experimentally verified “True Random Number Generator” that uses exclusively conventional CMOS technology as well as offering key improvements over previous designs in complexity, output bitrate, and power consumption. It uses the inherent randomness of telegraph noise in the channel current of a single CMOS transistor as an entropy source. For the first time multi-level and abnormal telegraph noise can be utilised, which greatly reduces device selectivity and offers much greater bitrates. The design is verified using a breadboard and FPGA proof of concept circuit and passes all 15 of the NIST randomness tests without any need for post-processing of the generated bitstream. The design also shows resilience against machine learning attacks performed by the LSTM neural network.

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mentioning

confidence: 99%

Random-telegraph-noise-enabled true random number generator for hardware security

Brown

Zhang

Zhou

et al. 2020

Sci Rep

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“…Notice, in any case, that the energy consumption needed to generate the random bits is not taken into account, since they can be generated in multiple ways. For instance, a 64-bit Mersenne RNG needs a lot of power to perform all the calculations that lead to the pseudorandom sequence of bits, but if we can use memristors for this task [41][42][43] this energy is drastically reduced, as well as the needed area. Additionally, a final ASIC implementation of the design could utilize some improvements, as extensively discussed in [33], that allow for exponential improvement of consumption.…”

Section: Discussionmentioning

confidence: 99%

“…It is worth noticing that the RNG is actually responsible of a large part of the total energy consumption, due to the large number of computations needed by the algorithm. This energy consumption could be addressed in the future by using memristors to generate the random bits, as proposed in [41][42][43].…”

Section: Implementing Chaotic Systems In Scmentioning

confidence: 99%

Stochastic Computing Implementation of Chaotic Systems

2021

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An exploding demand for processing capabilities related to the emergence of the Internet of Things (IoT), Artificial Intelligence (AI), and big data, has led to the quest for increasingly efficient ways to expeditiously process the rapidly increasing amount of data. These ways include different approaches like improved devices capable of going further in the more Moore path but also new devices and architectures capable of going beyond Moore and getting more than Moore. Among the solutions being proposed, Stochastic Computing has positioned itself as a very reasonable alternative for low-power, low-area, low-speed, and adjustable precision calculations—four key-points beneficial to edge computing. On the other hand, chaotic circuits and systems appear to be an attractive solution for (low-power, green) secure data transmission in the frame of edge computing and IoT in general. Classical implementations of this class of circuits require intensive and precise calculations. This paper discusses the use of the Stochastic Computing (SC) framework for the implementation of nonlinear systems, showing that it can provide results comparable to those of classical integration, with much simpler hardware, paving the way for relevant applications.

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“…Notice, in any case, that the energy consumption needed to generate the random bits is not taken into account, since they can be generated in multiple ways. For instance, a 64-bit Mersenne RNG needs a lot of power to perform all the calculations that lead to the pseudo-random sequence of bits, but if we can use memristors for this task [41][42][43] this energy is drastically reduced, as well as the needed area. Additionally, a final ASIC implementation of the design could utilize some improvements, as extensively discussed in [33], that allow for exponential improvement of consumption.…”

Section: Discussionmentioning

confidence: 99%

Stochastic Computing Implementation of Chaotic Systems

Camps¹,

Stavrinides²,

Picos³

2021

Preprint

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An exploding demand for processing capabilities related to the emergence of the IoT, AI and big data, has led to the quest for increasingly efficient ways to expeditiously process the rapidly increasing amount of data. These ways include different approaches like improved devices capable of going further in the more Moore path, but also new devices and architectures capable of going beyond Moore and getting more than Moore. Among the solutions being proposed, Stochastic Computing has positioned itself as a very reasonable alternative for low-power, low-area, low-speed, and adjustable precision calculations; four key-points beneficial to edge computing. On the other hand, chaotic circuits and systems appear to be an attractive solution for (low-power, green) secure data transmission in the frame of edge computing and IoT in general. Classical implementations of this class of circuits require intensive and precise calculations. This paper discusses the use of the SC framework for the implementation of nonlinear systems, showing that it can provide results comparable to those of classical integration, with much simpler hardware, paving the way for relevant applications.

show abstract

Memristor based Random Number Generator: Architectures and Evaluation

Cited by 29 publications

References 7 publications

Random-telegraph-noise-enabled true random number generator for hardware security

Random-telegraph-noise-enabled true random number generator for hardware security

Stochastic Computing Implementation of Chaotic Systems

Stochastic Computing Implementation of Chaotic Systems

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