Low Complexity Digit Serial Systolic Montgomery Multipliers for Special Class of ${\rm GF}(2^{m})$

Abstract

Montgomery Algorithm for modular multiplication with a large modulus has been widely used in public key cryptosystems for secured data communication. This paper presents a digit-serial systolic multiplication architecture for all-one polynomials (AOP) over GF(2 ) for efficient implementation of Montgomery Multiplication (MM) Algorithm suitable for cryptosystem. Analysis shows that the latency and circuit complexity of the proposed architecture are significantly less than those of earlier designs for same classes of polynomials. Since the systolic multiplier has the features of regularity, modularity and unidirectional data flow, this structure is well suited to VLSI implementations. The proposed multipliers have clock cycle latency of (2 1), where = is the word size and is the digit size. No digit serial systolic architecture based on MM algorithm over GF(2 ) is reported before. The architecture is also compared to two well known digit serial systolic architectures.

FPGA Realization of Low Register Systolic All-One-Polynomial Multipliers Over $GF(2^{m})$ and Their Applications in Trinomial Multipliers

“…All-one-polynomials (AOP)s and trinomials are two of the important irreducible polynomials being used [7][8][9][10][11], [17][18][19][20][21][22][23][24][25][26][27]. Due to security reasons, AOPs are usually not preferred for cryptosystem implementations though the AOP-based multipliers are quite simple and regular, while trinomial-based multipliers are more popular than AOP-based ones, as two trinomials have been recommended by the National Institute of Standards and Technology (NIST) for ECC implementation [5].…”

“…Many efforts have been reported to reduce the register-complexity in systolic multipliers based on irreducible AOPs and trinomials [7][8][9][10], [23][24][25][26][27]. A bitparallel AOP-based systolic multiplier has been introduced in [23].…”

“…The PCM of (31) only takes one XOR delay while the PCM of (27) takes two XORs' propagation time. To lower the critical-path delay, we have used two stage XOR operations to minimize the critical-path delay to one XOR delay (stage-I uses the least number of XOR gates required by (27), while stage-II realizes the rest of operations of (27) and (31) The internal structure of AOP-based computation core is shown in Fig. 5.2(b), where we T XN ) (if we choose the PEs from MS-II, the critical-path delay will be T XN ).…”

Robust secure charge-sharing symmetric adiabatic logic against side-channel attacks

“…Furthermore, the DPA attacks analyze different peaks of power consumption to reveal the secret key during encryption and decryption; hence, specific analysis of the various energy consumptions per input transitions and the analysis of the current-to-data dependency are required. The investigation process concentrates on individual AND and XOR logic, since they have been implemented in the AES hardware architecture and AES algorithm as well for addition and multiplication over secure S-Box structure design [14]- [16].…”

Low space‐complexity digit‐serial dual basis systolic multiplier over Galois field GF(2 m ) using Hankel matrix and Karatsuba algorithm

“…Typically, multipliers in GF(2 m ) can be classified into four types: bit-serial [3,24], bit-parallel [12,14,16,22,25,30], hybrid [15,17] and digit-serial [18,21] according to the way how the multiplier generates a result. Bit-serial multiplier iteratively generates a result bit per clock cycle so that it has the advantage of lower hardware cost.…”