We demonstrate the smallest FinFET SRAM cell size of 0.063 μm 2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE 2 ) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.
One of the challenges that single-electron transistors (SETs) face before they can be considered technologically useful is the charge offset drift. Recently, two different types of Si SETs were shown to have a drift of only 0.01e (the fundamental charge) over several days. Those devices came from one fabrication source. Here, we present the results for Si SETs fabricated by our group (a different source) demonstrating their operation as SETs. We confirm that the charge offset drift is less than 0.01e, demonstrating the lack of charge offset drift is generic to Si devices and not dependent on the fabrication source.
The authors have addressed the application of advanced ion beam-based analytical techniques to various physical characterization aspects in sub-32-nm semiconductor front-end-of-line materials and processes. We have presented the application of 18 O-isotope labeling in combination with SIMS depth profiling to follow O-migration in high-k/metal gate stacks. We have also demonstrated the application of complementary low-energy ion scattering and time-of-flight SIMS surface analysis to determine high-k thin film closure and growth mode for different deposition techniques. We have also proposed alternative Dynamic Secondary Ion Mass Spectrometry (DSIMS) protocols for the quantitative analysis of phosphorous ultra-shallow junctions, resulting in more accurate near-surface P-profile and in situ B-doped Si 1Àx Ge x epitaxial films with explicit correction of sputter and ionization yield variations as function of [Ge]. We have demonstrated the feasibility of backside SIMS on appropriate III-V highmobility channel stacks, resulting in unprecedented depth resolution at the source/drain metal-contact/III-V interface. Copyright
A novel fluorescence spectrometer and method for the simultaneous detection of multiple-fluorophore species in a no-moving-parts, instantaneous manner is described. In the reported embodiment of the instrument, a tapered Fabry-Perot filter is used to spatially encode the fluorescence spectrum from a multiple-dye-containing test sample. Using a pseudoinverse reconstruction algorithm, we spectrally decode the particle concentration for each dye specie in the test sample. Experimental results are reported along with a theoretical treatment of the method.
After decades of research, high-k metal gate has been successfully integrated into CMOS starting with the 45nm node. To continue scaling, the industry has chosen two integration approaches: FINFET with gate last and FDSOI with gate first. The FINFET with gate last integration was introduced into production at the 22nm node by Intel. The FDSOI with gate first integration was introduced into production at 28nm node by ST Microelectronics. There are some common factors impacting threshold voltage (Vt) on both integrations such as the high-k/metal gate film thickness and composition as well as the doping concentration. Beyond that, each integration approach has its own unique challenges that must be overcome to achieve targeted Vt and maintain Vt control. In this work we will highlight those unique challenges and discuss what knobs can be used to achieve the targeted Vt and maintain Vt control.
Planar fully-depleted silicon-on-insulator (FDSOI) technology potentially offers comparable transistor performance as FinFETs. pFET FDOSI devices are based on a silicon germanium (cSiGe) layer on top of a buried oxide (BOX). Ndoped interfacial layer (IL), high-k (HfO 2 ) layer and the metal gate stacks are then successively built on top of the SiGe layer. In-line metrology is critical in precisely monitoring the thickness and composition of the gate stack and associated underlying layers in order to achieve desired process control. However, any single in-line metrology technique is insufficient to obtain the thickness of IL, high-k, cSiGe layers in addition to Ge% and N-dose in one single measurement. A hybrid approach is therefore needed that combines the capabilities of more than one measurement technique to extract multiple parameters in a given film stack. This paper will discuss the approaches, challenges, and results associated with the first-in-industry implementation of XPS-XRF hybrid metrology for simultaneous detection of high-k thickness, IL thickness, N-dose, cSiGe thickness and %Ge, all in one signal measurement on a FDSOI substrate in a manufacturing fab. Strong correlation to electrical data for one or more of these measured parameters will also be presented, establishing the reliability of this technique.
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