(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI)

Triyoso, Dina H.; Carter, Rick; Kluth, J.; Luning, S.; Child, Amy; Wahl, Jeremy; Mulfinger, Bob; Punchihewa, Kasun; Kumar, Anil; Kang, Laegu; Sporer, R.; Chen, Xiaobo; Straub, S.; Bohra, Girish; Patil, Suraj; Zhang, Xing; Chen, Alex; Togo, M.; Pal, Rohit

doi:10.1149/06905.0103ecst

Cited by 3 publications

(3 citation statements)

References 4 publications

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“…FDSOI technology features improved the electrostatic controllability and channel carrier mobility of the gate, along with a decreased RDF. This technology possesses salient characteristics, such as a lower RDF with an undoped channel, eminent control of SCEs, higher carrier mobility, compatibility with planar processing library [72], lower mismatch variation, ultra-low-power applications [73][74][75], multi-V T option [76], and a good back gate biasing option, among others. All these features make FDSOI technology the best power/performance/cost tradeoff choice.…”

Section: Fdsoi Salient Characteristicsmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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After more than five decades, Moore’s Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

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Section: Fdsoi Salient Characteristicsmentioning

confidence: 99%

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

Radamson,

Miao,

Zhou

et al. 2024

Nanomaterials

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“…The UTBB is more flexible and have more management over speed and power because of the Body Bias technique which offers a threshold voltage control [12] while Tri-Gate has no body bias [13]. …”

Section: Flexibilitymentioning

confidence: 99%

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II

Mohsen¹,

Harb²,

Deltimple³

et al. 2017

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This is Part II of a two-part paper that explores the 28-nm UTBB FD-SOI CMOS and the 22-nm Tri-Gate FinFET technology as the better alternatives to bulk transistors especially when the transistor's architecture is going fully depleted and its size is becoming much smaller, 28-nm and above. Reliability tests of those alternatives are first discussed. Then, a comparison is made between the two alternative transistors comparing their physical properties, electrical properties, and their preferences in different applications.

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“…In the Gate Last integration, a dummy gate is created, followed by gate patterning and S/D formation. The dummy gate is then removed, and the HKMG and finally the contacts are manufactured (Figures and ). The operation of these very complex integration schemes requires comprehensive studies, in order to define the materials and material combinations with the appropriate properties and compatibility, and the optimum work function tuning metals.…”

Section: Introductionmentioning

confidence: 99%

The application of low energy ion scattering spectroscopy (LEIS) in sub 28‐nm CMOS technology

Dittmar

Triyoso

Erben

et al. 2017

Surface & Interface Analysis

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With the transition to ≤28-nm CMOS technology nodes, the surface analytical challenges with regard to steadily decreasing dimensions and still growing materials options raise the demand of high performing surface analysis techniques. Characterization of ultrathin films and multilayer stacks, especially in high-k metal gate stacks, by means of low energy ion scattering spectroscopy (LEIS) with its monolayer sensitivity has been established as a very useful analysis technique next to Auger electron spectroscopy, X-ray photoelectron spectroscopy, and time-of-flight secondary ion mass spectrometry. Questions regarding film nucleation, growth, coverage, and diffusion can be answered, thereby enabling those processes to be controlled appropriately.In this work, growth studies of ALD HfO 2 and TiN are shown, as well as film thickness determination based on surface spectra. PVD aluminum and lanthanum, acting as work function metals on the gate oxide, were deposited, and their film formation and closure were investigated.Further application fields of LEIS have emerged from the characterization of in-die features on patterned wafers. As presented on test arrays, it is possible to detect material deep in trenches. This is an advantage if residues need to be identified after etch or clean processes. KEYWORDS ALD, growth study, high-k metal gate, LEIS, PVD, work function metal 1 | INTRODUCTION CMOS technology progression beyond the 32-nm node requires the implementation of new materials such as high-k gate dielectrics and ultra thin metal gates. The scaling of conventional Poly SiON transistor structures is limited because of too high gate leakage currents. For 32nm CMOS and beyond, the needed short channel properties can only be reached by high-k metal gate (HKMG) technology. There are 2 integration approaches in implementing HKMG into CMOS: Gate First andGate Last. In the Gate First integration, as the name implies, the HKMG is formed first, followed by gate patterning, source/drain (S/D) and contact formation. In the Gate Last integration, a dummy gate is created, followed by gate patterning and S/D formation. The dummy gate is then removed, and the HKMG and finally the contacts are manufactured 1-6 ( Figures 1 and 2). The operation of these very complex integration schemes requires comprehensive studies, in order to define the materials and material combinations with the appropriate properties and compatibility, and the optimum work function tuning metals. Deposition processes, as well as cleaning and etching strategies, have to be developed or adapted. The properties of the ultra thin films in a HKMG stack strongly influence the transistor performance. Consequently, the introduction of atomic layer deposition (ALD) processes, replacing the established chemical, metal organic, and physical vapour deposition processes (CVD, MO-CVD, PVD), became a requirement. Key questions for the analyst are about nucleation, film growth, or diffusion. The transient regime in film formation of high-k gate oxide, metal gate, and the work f...

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(Invited) Factors Impacting Threshold Voltage in Advanced CMOS Integration: Gate Last (FINFET) vs. Gate First (FDSOI)

Cited by 3 publications

References 4 publications

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology

28-nm UTBB FD-SOI vs. 22-nm Tri-Gate FinFET Review: A Designer Guide—Part II

The application of low energy ion scattering spectroscopy (LEIS) in sub 28‐nm CMOS technology

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