22FDX TM is the industry's first FDSOI technology double-patterning steps required at the 16/14nm FinFET architected to meet the requirements of emerging mobile, technology nodes. Approximately 75% of the process steps Internet-of-Things (IoT), and RF applications. This platform are common with the 28nm platform enabling high yield achieves the power and performance efficiency of a 16/14nm capability. The gate-first High-K Metal Gate (HKMG) FinFET technology in a cost effective, planar device integration is used to ensure a low cost process flow [3]. A architecture that can be implemented with ~30% fewer typical cross-section of nFET and pFET devices is shown in masks. Performance comes from a second generation FDSOI Fig.1. All active devices are built on SOI whereas passive transistor, which produces nFET (pFET) drive currents of devices and select active devices, such as LDMOS, are 910μA/μm (856μA/μm) at 0.8V and 100nA/μm Ioff. For conventionally formed in the bulk substrate (Fig.2). In ultra-low power applications, it offers low-voltage operation addition to the introduction of FDSOI substrates, new process down to 0.4V Vmin for 8T logic libraries, as well as 0.62V and modules are introduced to support back-bias capability, 0.52V V min for high-density and high-current bitcells, ultra-passive device fabrication, enhanced device performance and low leakage devices approaching 1pA/µm Ioff, and body-technology scale factor (Fig.3). The introduction of a SiGe biasing to actively trade-off power and performance. channel for pFET devices by the condensation technique [4] Superior RF/Analog characteristics to FinFET are achieved and SOI thickness <7nm enable high DC drive currents. A including high f T /f MAX of 375GHz/290GHz and post STI hybrid etch process is used to form back gate 260GHz/250GHz for nFET and pFET, respectively. The contacts and enable the implementation of devices and taphigh f MAX extends the capabilities to 5G and millimeter wave cells in the bulk substrate (Fig.4). Dual in-situ doped epi (>24GHz) RF applications. processes (Si:P and SiGe:B) are formed in combination with a low-k spacer to ensure highly doped source/drain regions I. INTRODUCTION while maintaining low gate-to-drain capacitance (critical for Rising manufacturing costs and emerging applications RF applications). Technology CPP is scaled without adding requiring unparalleled energy efficiency are driving the need extra masking steps relative to the 28nm Front-End-of-Line. for new semiconductor device solutions. For the first time, Dual patterning techniques are used to scale M1/M2 pitch, an increase in the cost per die is observed with the leading to a logic/SRAM die scaling of 0.72x/0.83x relative to introduction of 16/14nm FinFET technologies due to the 28nm Poly/SiON technology node. increased process complexity and mask count. Cost sensitive B. Device Performance IoT and mobile applications are driving new requirements such as increased integration, advanced power management, Device construction utilizes either flip well (SLVT/LV...

This paper reviews the concepts, status and challenges for the DRAM scaling down to 40nm. The technologies that are discussed are the DRAM cell capacitor structures and materials, as well as the cell transistor structures.

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Thin ZrO2 films are of high interest as high-k material in dynamic random access memory (DRAM), embedded dynamic random access memory, and resistive random access memory as well as for gate oxides. Actually, ZrO2 is predicted to be the key material in future DRAM generations below 20 nm. Profound knowledge of pure and doped ZrO2 thin films, especially of the structural properties, is essential in order to meet the requirements of future devices. This paper gives a detailed overview about the structural properties of ZrO2 films in dependence of various process parameters. The study of atomic layer deposition (ALD) growth mechanisms of ZrO2 on a TiN-substrate in comparison to a Si-substrate covered with native oxide exhibits significant differences. Furthermore, the structural properti es crystallinity, surface roughness, and film stress are studied after the ALD deposition in dependence of the process parameters deposition temperature, layer thickness, and underlying substrate. Remarkable dependencies of the ZrO2 crystallization temperatures on the substrates are figured out. The structural properties after various annealing steps are monitored as well. The influence of doping by SiO2 and Al2O3 is studied, which is primarily used to keep the thin films amorphous during deposition

In this paper, we report reliability evaluation results for nanomixed amorphous ZrAlxOy and symmetrically or asymmetrically stacked ZrO2/Al2O3/ZrO2 dielectric thin films grown by atomic layer deposition method in cylindrical metal-insulator-metal capacitor structure. Clear distinctions between their I-V asymmetry and breakdown behavior were correlated with the differences in compositional modification of bottom interface, defect density, and conduction mechanism of the film stacks. The thermochemical molecular bond breakage model was found to explain the dielectric constant dependent breakdown field strength and electric field acceleration parameter of lifetime very well