We demonstrate the smallest FinFET SRAM cell size of 0.063 μm 2 reported to date using optical lithography. The cell is fabricated with contacted gate pitch (CPP) scaled to 80 nm and fin pitch scaled to 40 nm for the first time using a state-of-the-art 300 mm tool set. A unique patterning scheme featuring double-expose, double-etch (DE 2 ) sidewall image transfer (SIT) process is used for fin formation. This scheme also forms differential fin pitch in the SRAM cells, where epitaxial films are used to merge only the tight pitch devices. The epitaxial films are also used for conformal doping of the devices, which reduces the external resistance significantly. Other features include gate-first metal gate stacks and transistors with 25 nm gate lengths with excellent short channel control.
One of the challenges that single-electron transistors (SETs) face before they can be considered technologically useful is the charge offset drift. Recently, two different types of Si SETs were shown to have a drift of only 0.01e (the fundamental charge) over several days. Those devices came from one fabrication source. Here, we present the results for Si SETs fabricated by our group (a different source) demonstrating their operation as SETs. We confirm that the charge offset drift is less than 0.01e, demonstrating the lack of charge offset drift is generic to Si devices and not dependent on the fabrication source.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.