Write, erase and storage times in nanocrystal memories and the role of interface states

Wahl, Jeremy; Silva, H.; Gokirmak, Ali; Kumar, Arvind; Welser, J.J.; Tiwari, Sandip

doi:10.1109/iedm.1999.824173

Cited by 19 publications

(10 citation statements)

References 5 publications

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“…The time constant would differ from one Si-dot to the other due to the difference in the local thickness of the tunnel oxide, the size and shape of the silicon dot [10], the initial state of the emitting dot and of the surrounding dots. Moreover, also interface states in Si-dots [11] could play a role. Finally, as shown in Fig.…”

Section: Experiments and Discussionmentioning

confidence: 99%

Single Electron EffectsandStructuralEffects in Ultrascaled Silicon Nanocrystal Floating-Gate Memories

Molas

Salvo

Ghibaudo

et al. 2004

IEEE Trans. Nanotechnology

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In this paper, we present a nanometer-sized floating-gate memory device, fabricated on silicon-on-insulator substrate and using silicon nanocrystals as storage nodes. Single electron charging and discharging phenomena occurring at room temperature will be demonstrated and discussed by means of simple analytical models. A deeper investigation of the impact of critical dimensions of the memory cell (i.e., active area and channel width and length) on the device operation (in particular, memory programming window), performed on a large number of samples, will be reported. Qualitative explanations for the observed experimental behaviors will be given. Index Terms-Electron beam (e-beam) lithography, memories, quantum dots, silicon-on-insulator (SOI) technology.

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Section: Experiments and Discussionmentioning

confidence: 99%

Single Electron EffectsandStructuralEffects in Ultrascaled Silicon Nanocrystal Floating-Gate Memories

Molas

Salvo

Ghibaudo

et al. 2004

IEEE Trans. Nanotechnology

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“…This latter phenomenon is emphasized in the transconductance characteristic, where in the presence of Si-dots an additional local maximum appears for both up and down gate voltage sweeps. This feature indicates that a charge exchange occurs between the Si-dot and the channel when the gate voltage both sweeps up and down [4]. As shown in Fig.…”

Section: Transfer Characteristicsmentioning

confidence: 84%

“…3 for all the Si nano-crystal memories. In the Si-dot memory I d -V G curve, a hysteresis appears at low voltages and a hump, namely a dynamic change in the threshold voltage V th , in the high-voltage regime [4]. This latter phenomenon is emphasized in the transconductance characteristic, where in the presence of Si-dots an additional local maximum appears for both up and down gate voltage sweeps.…”

Section: Transfer Characteristicsmentioning

confidence: 95%

Investigation of charging/discharging phenomena in nano-crystal memories

Salvo

Ghibaudo²,

Pananakakis³

et al. 2000

Superlattices and Microstructures

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“…Most of the studies, including ours, have focused on the fabrication of metal-oxide-semiconductor ͑MOS͒ structures having semiconductor NCs. [5][6][7][8] Nevertheless, MOS-based memory devices fabricated with metal NCs, like Au, 9 Ni, [9][10][11] Ru, 12 W, 13 Pd, 14 RuO x , 17 TiN, 18 etc., are considered to be more advantageous for their higher density of states around the Fermi level, a wide range of available work function, stronger coupling with conduction channels, and smaller energy perturbation due to carrier confinement, [19][20][21][22] with the semiconductor counterpart. The use of metal NCs also makes it possible to use smaller operating voltages while obtaining better endurance characteristics and faster write/erase speeds with smaller fluctuations and interface states due to its high work function in comparison to its semiconductor counterpart.…”

mentioning

confidence: 99%

Memory Characteristics of Nickel Nanocrystals with High-k Dielectric Tunneling Barriers

Panda

Maikap

Dhar

et al. 2009

Electrochem. Solid-State Lett.

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The structural and electrical characteristics of Ni nanocrystals embedded in high-k HfO 2 have been studied. High-resolution transmission electron microscopy revealed the formation of tiny Ni nanocrystals, in the average diameter of ϳ8 nm size for the sample annealed at 1000°C for 5 min. Atomic force microscopy shows the deposition of uniform Ni nanocrystals on a HfO 2 layer. A good hysteresis memory window of ϳ2.1 V at sweeping gate voltage of Ϯ15 V was observed in optimized annealed samples. A maximum flatband voltage shift of 2.1 Ϯ 0.05 V was accomplished for the optimized sample. The retention and leakage current of the metal oxide semiconductor capacitors were also studied.Floating gate memory structures based on charge storage in discrete semiconductor and metal nanocrystals ͑NCs͒ have recently attracted renewed interest for their potential applications in nextgeneration flash memory devices. 1-14 Embedded NCs in the floating gate sandwiched between tunnel and control oxide layers are charged by direct-tunnel electrons from the channel to shift the device threshold.The downscaling of tunnel oxide thickness leads to reduction in operation voltage to attain faster programming and erasing speeds. Current efforts are focused on replacing conventional SiO 2 in the flash memory gate stack with high-dielectric-constant ͑high-k͒ materials 2,3,8,11,15,16 to remove the limitation of scaling trend in controlling the gate tunnel current for flash memory devices and to enhance retention performance. Most of the studies, including ours, have focused on the fabrication of metal-oxide-semiconductor ͑MOS͒ structures having semiconductor NCs. 5-8 Nevertheless, MOS-based memory devices fabricated with metal NCs, like Au, 9 Ni,[9][10][11] Ru, 12 W, 13 Pd, 14 RuO x , 17 TiN, 18 etc., are considered to be more advantageous for their higher density of states around the Fermi level, a wide range of available work function, stronger coupling with conduction channels, and smaller energy perturbation due to carrier confinement, 19-22 with the semiconductor counterpart. The use of metal NCs also makes it possible to use smaller operating voltages while obtaining better endurance characteristics and faster write/erase speeds with smaller fluctuations and interface states due to its high work function in comparison to its semiconductor counterpart. 19,20 Among other metals, nickel, which is attractive for complementary MOS technology as metal gate electrodes 21 and source drain engineered devices, 22 has not been fully explored for nonvolatile memories. Due to their high work function ͑ϳ4.9 eV͒, Ni NCs result in deep quantum wells for the trapping of charge carriers. Most of the work based on Ni NCs has been performed using conventional silicon dioxide as a tunneling barrier.In this article, we report the electrical characteristics of Ni NC MOS structures using HfO 2 as tunneling and control dielectrics. The effect of postdeposition annealing on memory and the structural, interfacial, and electrical properties of the floating gate memo...

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Write, erase and storage times in nanocrystal memories and the role of interface states

Cited by 19 publications

References 5 publications

Single Electron EffectsandStructuralEffects in Ultrascaled Silicon Nanocrystal Floating-Gate Memories

Single Electron EffectsandStructuralEffects in Ultrascaled Silicon Nanocrystal Floating-Gate Memories

Investigation of charging/discharging phenomena in nano-crystal memories

Memory Characteristics of Nickel Nanocrystals with High-k Dielectric Tunneling Barriers

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