Small silicon memories: confinement, single-electron,. and interface state considerations

Tiwari, Sandip; Wahl, Jeremy; Silva, Helena; Rana, Farhan; Welser, J.J.

doi:10.1007/s003390000553

Cited by 60 publications

(28 citation statements)

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“…To fully exploit their potential advantages over conventional floating gate memory, it is essential to control as accurately as possible Si nanocrystal size, depth distribution, and areal density, as well as nanocrystal surface passivation and oxide defect density in SiO 2 matrix, all in a process compatible with ultra-large-scale integration. Transmission electron microscopy ͑TEM͒ is the most widely used tool to characterize nanocrystal size and distribution with high resolution, [2][3][4] and sometimes electron diffraction is used to further substantiate the existence of crystallites. We have used a combination of contact-mode atomic force microscopy ͑AFM͒ and reflection high energy electron diffraction ͑RHEED͒ to identify the existence of nanocrystals, and used an ultrahigh vacuum scanning tunneling microscope ͑UHV STM͒ to estimate nanocrystal size and areal density.…”

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confidence: 99%

Probing the size and density of silicon nanocrystals in nanocrystal memory device applications

Feng

Dicken

et al. 2005

Applied Physics Letters

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Structural characterization via transmission electron microscopy and atomic force microscopy of arrays of small Si nanocrystals embedded in SiO 2 , important to many device applications, is usually difficult and fails to correctly resolve nanocrystal size and density. We demonstrate that scanning tunneling microscopy ͑STM͒ imaging enables a much more accurate measurement of the ensemble size distribution and array density for small Si nanocrystals in SiO 2 , estimated to be 2-3 nm and 4 ϫ 10 12 -3ϫ 10 13 cm −2 , respectively, in this study. The reflection high energy electron diffraction pattern further verifies the existence of nanocrystallites in SiO 2 . The present STM results enable nanocrystal charging characteristics to be more clearly understood: we find the nanocrystal charging measurements to be consistent with single charge storage on individual Si nanocrystals. Both electron tunneling and hole tunneling processes are suggested to explain the asymmetric charging/ discharging processes as a function of bias. © 2005 American Institute of Physics. ͓DOI: 10.1063/1.1852078͔Silicon nanocrystal memories 1 have attracted much attention in recent years. To fully exploit their potential advantages over conventional floating gate memory, it is essential to control as accurately as possible Si nanocrystal size, depth distribution, and areal density, as well as nanocrystal surface passivation and oxide defect density in SiO 2 matrix, all in a process compatible with ultra-large-scale integration. Transmission electron microscopy ͑TEM͒ is the most widely used tool to characterize nanocrystal size and distribution with high resolution, 2-4 and sometimes electron diffraction is used to further substantiate the existence of crystallites. We have used a combination of contact-mode atomic force microscopy ͑AFM͒ and reflection high energy electron diffraction ͑RHEED͒ to identify the existence of nanocrystals, and used an ultrahigh vacuum scanning tunneling microscope ͑UHV STM͒ to estimate nanocrystal size and areal density. Compared with TEM, using RHEED with very small incident angle enables high sensitivity to nanocrystal structure, and the resolution of STM is sufficiently high to detect nanometer size crystallites. The charging, discharging, and retention behaviors of the MOS capacitor nanocrystal memory structures were investigated by capacitance-voltage ͑C -V͒ measurements. The results obtained from both structural and electrical characterization are combined for complete analysis of nanocrystal floating gate memory devices made via Si ion implantation.The samples investigated consist of 15 nm dry oxide grown on p-type silicon substrate ͑N A =3ϫ 10 18 cm −3 ͒ implanted with 5 keV Si + ions to a fluence of 1.27 ϫ 10 16 cm −2 . The samples were annealed at 1080°C for 5 min in an atmosphere containing 2 % O 2 to allow formation of Si nanocrystals. Control samples without implantation were fabricated with the same structure and treated with the same condition as samples with nanocrystals. Cross-sectional high resolution...

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confidence: 99%

Probing the size and density of silicon nanocrystals in nanocrystal memory device applications

Feng

Dicken

et al. 2005

Applied Physics Letters

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“…The replacement of this floating-gate by a layer of discrete Si nanocrystals (NCs) [1] improves the performance of flash memories substantially [2]. The reduced probability for a complete discharging of the multi-dot floating-gate by oxide defects allows thinner tunnel oxides.…”

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Multi-dot floating-gates for nonvolatile semiconductor memories: Their ion beam synthesis and morphology

Müller

Bonafos

Heinig

et al. 2004

Applied Physics Letters

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Scalability and performance of current flash memories can be improved substantially by replacing the floating poly-Si gate by a layer of Si dots. This multi-dot layer can be fabricated CMOS-compatibly in very thin gate oxide by ion beam synthesis (IBS). Here, we present both experimental and theoretical studies on IBS of multidot layers consisting of Si nanocrystals (NCs). The NCs are produced by ultra low energy Si + ion implantation, which causes a high Si supersaturation in the shallow implantation region. During post-implantation annealing, this supersaturation leads to phase separation of the excess Si from the SiO 2 . Till now, the study of this phase separation process suffered from the weak Z contrast between Si and SiO 2 in Transmission Electron Microscopy (TEM). Here, this imaging problem is resolved by mapping Si plasmon losses with a Scanning Transmission Electron Microscopy equipped with a parallel Electron Energy Loss Spectroscopy system (PEELS-STEM). Additionally, kinetic lattice Monte Carlo simulations of Si phase separation have been performed and compared with the experimental Si plasmon maps. It has been predicted theoretically that the morphology of the multidot Si floating-gate changes with increasing ion fluence from isolated, spherical NCs to percolated spinodal Si pattern. These patterns agree remarkably with PEELS-STEM images. However, the predicted fluence for spinodal patterns is lower than the experimental one. Because oxidants of the ambient atmosphere penetrate into the as-implanted SiO 2 , a substantial fraction of the implanted Si might be lost due to oxidation.Metal-Oxide-Silicon Field-Effect-Transistors (MOSFETs) with an electrically isolated ("floating") gate layer embedded in the gate oxide are currently used as flash memories. The replacement of this floating-gate by a layer of discrete Si nanocrystals (NCs) [1] improves the performance of flash memories substantially [2]. The reduced probability for a complete discharging of the multi-dot floating-gate by oxide defects allows thinner tunnel oxides. In turn, the floatinggate will be charged/discharged by quantum mechanical direct electron tunneling (instead of defect-generating FowlerNordheim tunneling). The memory operation voltage can be reduced and scalability is improved. Using ion beam synthesis, the multi-dot floating-gate can be fabricated along with standard CMOS processing [3]. Si + ions are implanted at ultra low energies into the gate oxide, causing there a high Si supersaturation. During post-implantation annealing, this Si supersaturation leads to phase separation of elemental Si from SiO 2 [4]. Imaging this phase separation process is difficult. Till now, Transmission Electron Microscopy (TEM) has suffered from weak Z contrast between Si and SiO 2 phases. Recently, this problem was partially overcome by Fresnel imaging using under-focused bright field conditions [5]. Thus, the distance of the layer of phase separated Si from the transistor channel could be determined [6,7]. However, this technique fails to resol...

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“…For the latter, a clear staircase of the threshold voltage shift was presented at room temperature [41]. However, such discrete DV th becomes clear only at low temperature for the former [66]. The low temperature requirement could be due to a large percolation current flowing through the wide channel at high temperature.…”

Section: Memory Operationsmentioning

confidence: 99%

Silicon Nanocrystal Flash Memory

Oda

Huang

2010

Silicon Nanocrystals

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Small silicon memories: confinement, single-electron,. and interface state considerations

Cited by 60 publications

References 1 publication

Probing the size and density of silicon nanocrystals in nanocrystal memory device applications

Probing the size and density of silicon nanocrystals in nanocrystal memory device applications

Multi-dot floating-gates for nonvolatile semiconductor memories: Their ion beam synthesis and morphology

Silicon Nanocrystal Flash Memory

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