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International audienceWe investigate the occurrence of Multiple Bit Upsets in commercial SRAMs of 4 Mbits and 32 Mbits when irradiated with neutrons. The devices were irradiated at TSL facility with QMN beams of energies from 50 MeV to 180 MeV. Experimental data demonstrate that the dynamic-stress increases SRAMs sensitivity as well as MBUs occurrence for both the memory types. We also show that both SEU and MBU cross section may depend on memory architecture and memory utilization

This paper studies the voltage and current behavior of Gate Oxide Short faults due to pinhole in the gate oxide. The objective of this paper is to give a detailed analysis of the behavior of the GOS defect taking into account the random parameter of the defect such as the GOS resistance, the GOS location and the GOS size. Because an accurate analysis is desired, the bi-dimensional array will be used. Because a complete analysis is desired, we derive characteristic of the GOS as a function of the GOS resistance, location and size. Finally, because a realistic analysis is desired the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit.

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In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in details using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.