Resistive Bridge fault model evolution from conventional to ultra deep submicron

Polian, Ilia; Engelke, Piet; Becker, Bernd; Kundu, Sandip; Galliere, Jean-Marc; Renovell, Michel

doi:10.1109/vts.2005.72

Cited by 46 publications

(34 citation statements)

References 21 publications

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“…Logic threshold voltage is defined as the gate input voltage at which the gate output voltage is equal to V dd 2 , while all other inputs of the gate are at non-controlling value(s) [11]. This calculation is necessary, since L th is needed for critical resistance calculation of a given fault-site and is calculated using BSIM4 transistor 1 Mobility varies due to variation in effective strain in a strained silicon process [6].…”

Section: Proposed Variation-aware Bridge Fault Modeling Techniquementioning

confidence: 99%

“…Resistive bridge fault (RBF) represents a major class of defects in deep-submicron (DSM) CMOS and have received increased attention on modeling and simulation [1]. Manufacturing test employs fault models for testing digital circuits, which are meant to emulate the physical behaviour of a defect at device level.…”

Section: Introductionmentioning

confidence: 99%

“…It uses curve fitting to match results with SPICE data to achieve high accuracy. To account for DSM behaviour, a more advanced transistor model (BSIM4) is used to compute bridge critical resistance [1]. These two RBF models [1], [2] are intended for designs operating in nominal conditions, however due to continuous scaling of CMOS, DSM designs are affected by process variation [3], [4].…”

Section: Introductionmentioning

confidence: 99%

“…To account for DSM behaviour, a more advanced transistor model (BSIM4) is used to compute bridge critical resistance [1]. These two RBF models [1], [2] are intended for designs operating in nominal conditions, however due to continuous scaling of CMOS, DSM designs are affected by process variation [3], [4]. Fabrication process variation is mainly due to sub-wavelength lithography, random dopant distribution, line edge roughness and stress engineering [5], [6].…”

Section: Introductionmentioning

confidence: 99%

“…1, I 1 , I 2 and I 3 ). The effect of process variation is modeled by incorporating fluctuations in three transistor parameters: gate length (L), threshold voltage (V th ) and effective mobility (µ ef f ) 1 as reported in a recent study [6]. The effect of voltage variation is directly applied by changing the supply voltage; finally, the effect of temperature variation is incorporated by using temperature dependent transistor models of threshold voltage, mobility and saturation velocity using BSIM4 [10].…”

Section: Introductionmentioning

confidence: 99%

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A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects

Zhong

Khursheed

Al-Hashimi

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Abstract-Recent research has shown that tests generated without taking process variation into account may lead to loss of test quality. At present there is no efficient device-level modeling technique that models the effect of process variation on resistive bridge defects. This paper presents a fast and accurate technique to achieve this, including modeling the effect of voltage and temperature variation using BSIM4 transistor model. To speedup the computation time and without compromising simulation accuracy (achieved through BSIM4) two efficient voltage approximation algorithms are proposed for calculating logic threshold of driven gates and voltages on bridged lines of a fault-site to calculate bridge critical resistance. Experiments are conducted on a 65-nm gate library (for illustration purposes), and results show that on average the proposed modeling technique is more than 53 times faster and in the worst case, error in bridge critical resistance is 2.64% when compared with HSPICE.Index Terms-Resistive bridge fault, fault model, manufacturing test, process variation.

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Section: Proposed Variation-aware Bridge Fault Modeling Techniquementioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 3 more Smart Citations

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects

Zhong

Khursheed

Al-Hashimi

2011

IEEE Trans. Comput.-Aided Des. Integr. Circuits Syst.

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Machine Learning Support for Logic Diagnosis and Defect Classification

Wunderlich

2022

Machine Learning Support for Fault Diagnosis of System-on-Chip

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How Many Test Vectors We Need to Detect a Bridging Fault?

Favalli

Dalpasso

2008

J Electron Test

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The growing dispersion of ICs’ parameters poses relevant uncertainties on gate output conductances and logic thresholds which play a main role in bridging fault detection. In this evolving context, the quality of fault simulation and test generation tools making use of nominal parameters should be verified. To analyze this problem we have studied bridging fault detection in combinational ICs in the presence of growing variations of IC’s parameters. Results show that a single test is not sufficient to ensure acceptable escape probabilities. Conversely, the minimal number of test vectors required to provide a null escape probability is upper bounded with respect to variations in the standard deviation of IC’s parameters. This result has been verified by means of Monte Carlo electrical level simulation. We propose a method to derive these minimal test sets in the case of low frequency tests. A fault simulator and a test generator have been developed supporting the search of minimal test sets targeting a null escape probability. These tools have been applied to a set of combinational benchmarks

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Resistive Bridge fault model evolution from conventional to ultra deep submicron

Cited by 46 publications

References 21 publications

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects

A Fast and Accurate Process Variation-Aware Modeling Technique for Resistive Bridge Defects

Machine Learning Support for Logic Diagnosis and Defect Classification

How Many Test Vectors We Need to Detect a Bridging Fault?

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