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An ecient package for construction of and operation on ordered K r onecker F unctional D e cision Diagrams (OKFDD) is presented. OKFDDs are a generalization o f OBDDs and OFDDs and as such provide a more c ompact representation of the functions than either of the two decision diagrams. In this paper b asic properties of OKFDDs and their ecient representation and manipulation a r e presented. Based on the comparison of the three d e cision diagrams for several b enchmark functions, a 25% improvement in size over OBDDs is observed for OKFDDs.

We present a novel method for computing reachability probabilities of parametric discrete-time Markov chains whose transition probabilities are fractions of polynomials over a set of parameters. Our algorithm is based on two key ingredients: a graph decomposition into strongly connected subgraphs combined with a novel factorization strategy for polynomials. Experimental evaluations show that these approaches can lead to a speed-up of up to several orders of magnitude in comparison to existing approaches. PreliminariesDefinition 1 (Discrete-time Markov chain). A discrete-time Markov chain (DTMC) is a tuple D = (S, I, P ) with a non-empty finite set S of states, an initial

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We present a uniform signature-based approach to compute the most popular bisimulations. Our approach is implemented symbolically using BDDs, which enables the handling of very large transition systems. Signatures for the bisimulations are built up from a few generic building blocks, which naturally correspond to efficient BDD operations. Thus, the definition of an appropriate signature is the key for a rapid development of algorithms for other types of bisimulation. We provide experimental evidence of the viability of this approach by presenting computational results for many bisimulations on real-world instances. The experiments show cases where our framework can handle state spaces efficiently that are far too large to handle for any tool that requires an explicit state space description.

Test application at reduced power supply voltage (or VLV testing) is a cost-effective way to increase the defect coverage of a test set. Resistive short defects are a major contributor to this coverage increase. Using a probabilistic model of these defects, we quantify the coverage impact of VLV testing for different voltages. When considering the coverage increase, we differentiate between defects missed by the test set at nominal voltage and undetectable defects (flaws) detected by VLV testing. In our analysis, the performance degradation of the device caused by lower power supply voltage is accounted for. Furthermore, we describe a situation in which defects detected by conventional testing are missed by VLV testing and quantify the resulting coverage loss. We report the numbers on the increased defect coverage, flaw coverage, and coverage loss for ISCAS circuits.

Abstract. Many optimisation problems in circuit design, in the following also refereed to as VLSI CAD, consist of mutually dependent sub-problems, where the resulting solutions must satisfy several requirements. Recently, a new model for Multi-Objective Optimisation (MOO) for applications in Evolutionary Algorithms (EAs) has been proposed. The search space is partitioned into so-called Satisfiability Classes (SCs), where each region represents the quality of the optimisation criteria. Applying the SCs to individuals in a population a fitness can be assigned during the EA run. The model also allows the handling of infeasible regions and restrictions in the search space. Additionally, different priorities for optimisation objectives can be modelled. In this paper, the model is studied in further detail. Various properties are shown and advantages and disadvantages are discussed. The relations to other techniques are presented and experimental results are given to demonstrate the efficiency of the model.