Simulating Resistive-Bridging and Stuck-At Faults

Abstract

We present a simulator for resistive bridging and stuck-at faults. In contrast to earlier work, it is based on electrical equations rather than table look-up, thus exposing more flexibility. For the first time, simulation of sequential circuits is dealt with; reciprocal action of fault effects in current time frame and earlier time frames is elaborated on for different bridge resistances. Experimental results are given for resistive bridging and stuck-at faults in combinational and sequential circuits. Different definitions of fault coverage are listed and quantitative results with respect to all these definitions are given for the first time.

Thread-Parallel Integrated Test Pattern Generator Utilizing Satisfiability Analysis

“…Bridging faults with non-zero bridge resistance may impact the behavior of a digital circuit in a non-trivial way [15,33]. In general, a short defect with a non-zero resistance R sh between interconnects a and b imposes intermediate voltages V a and V b between 0 and V D D on the affected interconnects.…”

“…First, defects in nanoscale manufacturing technologies may not be described adequately by stuck-at faults [2]. Non-standard fault models such as resistive bridging faults [15,33] or interconnect opens [23,37] may impose very specific conditions on the lines in the circuit, which are, in many cases, impossible to satisfy, so the fault is undetectable. Second, redundant structures are being increasingly used to enhance circuit reliability and yield [40,46].…”

On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing

“…The analysis in this paper is based on the resistive bridging fault (RBF) model from [2, 3,12], which uses the concepts of critical resistance and analogue detectability interval. This section will first review the base RBF model and then discuss the metrics for detection under non-nominal conditions.…”

“…The remainder of the paper is organized as follows: the next session briefly reviews the basic RBF fault model from [12], describes the metrics for quantifying the coverage under non-nominal conditions (i.e., either reduced voltage, or reduced temperature, or both) and addresses the electrical model for low-temperature and low-voltage test. Note that the RBF model and the temperature/voltage model that we employ is valid only for CMOS ICs but not for circuits with bipolar transistors.…”

Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test

“…Process variations have a negative impact on test performance and various test techniques have been developed to improve resistive bridge detection [6]. In [7] a method is presented to determine the critical resistance of a bridge defect whose value is the limit between a correct logic value and a fault. In [8] the advantage of test application at reduced V DD was analyzed, showing that resistive bridge defects fault coverage depends on the supply voltage applied during test.…”