Resistive bridge defect detection enhancement under parameter variations combining Low VDD and body bias in a delay based test

Villacorta, Hector; Champac, Victor; Bota, S.; Segura, J.

doi:10.1016/j.microrel.2012.04.001

Cited by 8 publications

(2 citation statements)

References 26 publications

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“…Test time also increases when Low VDD and RBB is used. However, the ratio of improvement on test detection of resistive bridges with respect to the test time penalty is higher [13]. This result lead to evince the feasibility of the technique.…”

Section: B Impact Of Body Bias On Bridge Defect Detectionmentioning

confidence: 99%

“…In [12] a low voltage test combined to substrate biasing was proposed showing that this method could detect defects that were not detected by IDDQ tests. In [13] we investigated the effectiveness of lowering VDD and applying reverse body bias on the detection of resistive bridge defects in presence of process variations. This analysis was made in a lO-inverter chain.…”

Section: Introductionmentioning

confidence: 99%

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Bridge defect detection in nanometer CMOS circuits using Low VDD and body bias

Villacorta

Garcia-Gervacio

Champac

et al. 2013

2013 14th Latin American Test Workshop - LATW

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Bridge defects are an important manufacturing defect that may escape test. Even more, it has been shown that in nanometer regime, process variations pose important challenges for traditional delay test methods. Therefore, ad vances in test methodologies to deal with nanometer issues are required. In this work the feasibility of using Low VDD and body bias in a delay based test to detect resistive bridge defects in CMOS nanometer circuits is analyzed. The detection of bridge defects using a delay based test in nanometer circuits is strongly influenced by: 1) spatial correlation of the process parameters such as length, width and oxide thickness of the transistor, (2) random placement of dopants, and (3) the signal correlation due to reconvergent paths. Because of this, in this work a Statistical Timing Analysis Framework (STAF) is used to analyze the possibilities of detection of bridge defect using a delay based test. The STAF considers different values of VDD and body bias. The detection of the bridge defects of a circuit is computed by the Statistical Fault Coverage that gives a more realistic measure of the degree of detection of the defect. This methodology is applied to some ISCAS benchmark circuits implemented in a 65nm CMOS technology. The obtained results show the feasibility of the proposed methodology.

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Section: B Impact Of Body Bias On Bridge Defect Detectionmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%