Modeling gate oxide short defects in CMOS minimum transistors

Abstract

In this paper a new model is proposed for Gate Oxide Short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in details using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.

Oscillation-Based Test Applied to a Wideband CCII

“…The state-of-the-art in OBT testing [8][9][10]14] uses 10 Ω resistors to represent short circuit faults and 10 MΩ resistors to represent open circuit faults. As open and short circuits on-chip may assume a wide variety of impedance values [18], it would be prudent to analyse the effect of substituted impedance value variation on the OBT technique.…”

Pseudo Transistor Matrix for Defect Density Extraction of Gate Oxide Shorts

“…Dependent current source model and diode-resistance model were developed by Rodriguez [2][3]. Renovell proposed bi-dimensional model, linear nonsplit MOS model, and nonlinear nonsplit model [4][5][6]. In addition, Yassine presented a method that differentiated gate oxide failures from silicide bridging between gate and source/drain [7].…”

Gate-Oxide-Short Defect Analysis and Fault Modeling Based on FinFET's 3D Structure

“…Therefore, it is important to develop accurate defect models that can be used in obtaining reliable fault models and practical test patterns. There are two types of GOS model for MOSFETs, split and non-split [63]. In the split model, a bidimensional array of transistors are used as an electrical model of a defect-free transistor, Figure 3.2 (a).…”

“…The non-split models are categorized in two groups, linear and non-linear [63]. In [32], authors have proposed the nonlinear non-split model shown in Figure 3.4 (a).…”