Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI -- LVT and RVT Configurations

Karel, Amit; Comte, Mariane; Galliere, Jean-Marc; Azaïs, Florence; Renovell, Michel

doi:10.1109/isvlsi.2016.102

Cited by 11 publications

(6 citation statements)

References 7 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…In order to reduce the influence of the high threshold voltage, the input transistors of both the CSA and the pulse shaper modules have been optimized based on conventional LVT operations [ 57 ]. In fact, LVT devices have a higher current density and transconductance than regular threshold voltage (RVT) transistors for the same bias conditions, which enforces the previous suitable applications, commented [ 58 , 59 ]. Furthermore, LVT transistors have higher transconductance efficiency, so for low power applications, LVT MOSFETS are recommended.…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 88%

“…RVT devices have lower VDSsat than LVT MOSFETs. The fact that for applications that need lower supply voltages and do not need require high gains RVT devices are a good choice [ 58 , 59 ]. In addition, LVT transistors present slightly lower parasitic capacitances than RVT transistors, which involves that LVT devices are more suitable for high-frequency applications than the RVT [ 58 , 59 , 60 ].…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

“…The fact that for applications that need lower supply voltages and do not need require high gains RVT devices are a good choice [ 58 , 59 ]. In addition, LVT transistors present slightly lower parasitic capacitances than RVT transistors, which involves that LVT devices are more suitable for high-frequency applications than the RVT [ 58 , 59 , 60 ]. Taking into account the trade-off between transistor size and mismatch, we perform optimal transistor sizing/matching with a parallel arrangement of the devices to reduce the parasitic and mismatch effects, canceling, therefore, the short circuit power generated by those parasitic [ 53 , 55 , 60 ] and achieved 8.72 µW of maximum power consumption.…”

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

See 2 more Smart Citations

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Jérôme

Evariste

Bernard

et al. 2021

Sensors

View full text Add to dashboard Cite

The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.

show abstract

Section: Simulation Outcomes and Discussionmentioning

confidence: 88%

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

Section: Simulation Outcomes and Discussionmentioning

confidence: 99%

See 1 more Smart Citation

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Jérôme

Evariste

Bernard

et al. 2021

Sensors

View full text Add to dashboard Cite

show abstract

“…According to the principle and electrical characteristics of FDSOI devices, the physical parameters of devices, such as gate length, buried oxygen layer thickness, bulk doping concentration and metal work function, have great influence on the I d -V g curve of devices [19][20][21][22]. Therefore, these four physical parameters are taken as the input of I d -V g curve prediction.…”

Section: Transfer Characteristic Curve Predictionmentioning

confidence: 99%

Prediction of electrical properties of FDSOI devices based on deep learning

et al. 2022

View full text Add to dashboard Cite

Fully depleted Silicon on insulator technology (FDSOI) is proposed to solve the various non-ideal effects when the process size of integrated circuits is reduced to 45nm. The research of traditional FDSOI devices is mostly based on simulation software, which requires a lot of calculation and takes a long time. In this paper, a deep learning based electrical characteristic prediction method for FDSOI devices is proposed. Deep learning algorithm is used to train the simulation data and establish the relationship between the physical parameters and electrical characteristics of the device. The network structure used in the experiment has high prediction accuracy. The mean square error of electrical parameters and transfer characteristic curve is only 4.34×10-4 and 2.44×10-3 respectively. This method can quickly and accurately predict the electrical characteristics of FDSOI devices without microelectronic expertise. In addition, this method can be extended to study the effects of various physical variables on device performance, which provides a new research method for the field of microelectronics.

show abstract

“…The value of n coefficient, also called "body factor" is around 85 mV/V for a pristine device [14]. For this study we have used two types of FDSOI transistors [15]: low threshold voltage (LVT) and regular threshold voltage (RVT) transistors, depicted in Figure 1. RVT transistors are built on a standard well while LVT ones are built on a flip well.…”

Section: B Back-gate Biasmentioning

confidence: 99%

A Mixed Method to Mitigate the TID Effects on 28nm FDSOI Transistors

Acuna

Armani

Slimani

et al. 2020

2020 20th European Conference on Radiation and Its Effects on Components and Systems (RADECS)

View full text Add to dashboard Cite

In this work we propose a mixed method to mitigate the effects of Total Ionizing Dose (TID) on 28nm Fully-Depleted Silicon-On-Insulator (FDSOI) MOSFETs exposed to 60 Co gamma radiation at two different dose rates. This new thermal-electrical method uses thermal regeneration by applying rapid annealing cycles in addition to threshold voltage modulation inherent in FDSOI technology. Applying this methodology could enhance the transistor reliability during a mission in radiative environments.

show abstract

Impact of VT and Body-Biasing on Resistive Short Detection in 28nm UTBB FDSOI -- LVT and RVT Configurations

Cited by 11 publications

References 7 publications

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

An 8.72 µW Low-Noise and Wide Bandwidth FEE Design for High-Throughput Pixel-Strip (PS) Sensors

Prediction of electrical properties of FDSOI devices based on deep learning

A Mixed Method to Mitigate the TID Effects on 28nm FDSOI Transistors

Contact Info

Product

Resources

About