This paper proposed a design of low-voltage Dynamic Comparator using 90 nm PTM CMOS technology for high-speed and Lower-power Analog to Digital Converter (ADC) applications. The double tail structure is employed as based for design new comparator with positive feedback due to best behavior in low-voltage that allows low delay time; decreases the offset voltage and power dissipation. Simulation results are presented with sampling frequency of 10GH Z. These results are also compared with earlier works interms of their delay time, power dissipation and offset voltage. The proposed comparator shows 5.7 mV offset which is small when compared to other dynamic comparators and preamplifier based comparators.
Abstract:The treatment of inoperable cancers in the therapy terminal in Lanzhou-China, which is located at the Institute of Modern Physics (IMP), permits to work on the actual front-end readout. The availability of detailed noise spectral density characteristics for the OPA amplifier helps to develop the noise error analysis for high-resolution. This work focused on the noise model of the detector-preamplifier, which presents the low noise circuit schematic of the Transimpedance (TIA). Considering the parasitical influences, we develop a new approach to detect the weak signals based on resonant frequency, 1/√L 1 (C 1 +C GS ). In addition, the system eliminates leakage current in the reset switch and reduces the charge injection occur from the switches in the Gated Integrator (GI) and the configuration switch is made especially with two transmission gates switches, in series, with a grounded MOS switch, attached to the node between the two transmission gates switches and the linearity almost good.
The front-end electronics (FEE) of the Compact Muon Solenoid (CMS) is needed very low power consumption and higher readout bandwidth to match the low power requirement of its Short Strip application-specific integrated circuits (ASIC) (SSA) and to handle a large number of pileup events in the High-Luminosity Large Hadron Collider (LHC). A low-noise, wide bandwidth, and ultra-low power FEE for the pixel-strip sensor of the CMS has been designed and simulated in a 0.35 µm Complementary Metal Oxide Semiconductor (CMOS) process. The design comprises a Charge Sensitive Amplifier (CSA) and a fast Capacitor-Resistor-Resistor-Capacitor (CR-RC) pulse shaper (PS). A compact structure of the CSA circuit has been analyzed and designed for high throughput purposes. Analytical calculations were performed to achieve at least 998 MHz gain bandwidth, and then overcome pileup issue in the High-Luminosity LHC. The spice simulations prove that the circuit can achieve 88 dB dc-gain while exhibiting up to 1 GHz gain-bandwidth product (GBP). The stability of the design was guaranteed with an 82-degree phase margin while 214 ns optimal shaping time was extracted for low-power purposes. The robustness of the design against radiations was performed and the amplitude resolution of the proposed front-end was controlled at 1.87% FWHM (full width half maximum). The circuit has been designed to handle up to 280 fC input charge pulses with 2 pF maximum sensor capacitance. In good agreement with the analytical calculations, simulations outcomes were validated by post-layout simulations results, which provided a baseline gain of 546.56 mV/MeV and 920.66 mV/MeV, respectively, for the CSA and the shaping module while the ENC (Equivalent Noise Charge) of the device was controlled at 37.6 e− at 0 pF with a noise slope of 16.32 e−/pF. Moreover, the proposed circuit dissipates very low power which is only 8.72 µW from a 3.3 V supply and the compact layout occupied just 0.0205 mm2 die area.
Power consumption and image resolution are the major concerned while designing modern readout integrated circuits (ROICs) of Cadmium-Telluride (CdTe)/Cadmium-Zinc-Telluride (CdZnTe) sensors for nuclear magnetic resonance imaging (MRI) and positron emission tomography (PET) applications.The key ROIC element, namely, preamplifier, must be monolithically integrated to the sensor chip and should guarantee low noise, low power, and high linearity along with assuring higher conversion gain and less chip area. A power immune, linear charge sensitive preamplifier (CSP) with a custom leakage current compensation feedback for (CdTe)/CdZnTe sensors is designed. A maximum power consumption of 120 μW, stable against process voltage and temperature (PVT) variations, is achieved. The compensation module cancels out current noise generated at the output of the circuit, lowering the power spectral density of about 84.26% than that of similar architectures, thus improving the signal-to-noise ratio (SNR) at the CSP output by a factor of 6.31.In turns, it injects about 100 pA of input direct-current (DC) current and compensates the sensor leakage current therefore. Two input dynamics of (0.25-10) and (10.01-20)fC are achieved, providing two conversion factors of 23.06 and 19.00 mV/fC with 2.4% and 0.58% nonlinearity errors, respectively, using 1 pF sensor capacitance. Noise performance of the circuit is improved with 47.5 e-rms and 62.46eÀrms of equivalent noise charge (ENC) depending upon the input dynamic. The design is validated by Monte Carlo simulations and PVT analysis implemented in 65 nm complementary metal-oxide semiconductor (CMOS) process, assuring a chip area of only 0.000246 mm 2 .
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