Abstract-Despite significant advances in structure and material optimization, poor erase (E) speeds and high retention charge loss remain the challenging issues for charge trap Flash (CTF) memories. In this paper, the dependence of SANOS memory performance and reliability on the composition of silicon nitride (SiN) layer is extensively studied. The effect of varying the Si:N ratio on program (P)/E and retention characteristics is investigated. SiN composition is shown to significantly alter the electron and hole trap properties. Varying the SiN composition from N-rich (N + ) to Si-rich (Si + ) lowers electron trap depth but increases hole trap depth, causing lower P state saturation but significant overerase, resulting in an enhanced memory window. During retention, P state charge loss depends on thermal emission followed by the tunneling out of electrons mostly through tunnel dielectric, which becomes worse for Si + SiN. Erase state charge loss mainly depends on hole redistribution under the influence of internal electric fields, which improves with Si + SiN. This paper identifies several important performances versus reliability tradeoffs to be considered during the optimization of SiN layer composition. It also explores the option for CTF optimization through the engineering of SiN stoichiometry for multilevel cell NAND Flash applications.Index Terms-Charge trap Flash (CTF), program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

The field-measured current-voltage (I-V) curves of photovoltaic (PV) modules need to be corrected to Standard Test Conditions (STC) in order to estimate the degradation rates. STC correction procedures have various attributes such as accuracy, requirement of minimum number and types of I-V curves, required irradiance range, and the type of correction (specific points or entire I-V curve) that determine their optimality for specific applications. This paper presents the investigation of accuracy and constraints of six different STC correction procedures for high-throughput field I-V measurements through experimental and simulation studies. Following STC correction procedures are considered in this paper: IEC 60891-Procedure 1, IEC 60891-Procedure 2, Modified IEC 60891-Procedure 1, Standard Irradiance and Desired Temperature (SIDT) procedure, Anderson procedure, and Voltage-Dependent Temperature Coefficient (VDTC) Procedure. Eight different simulation models for predicting the performance of PV modules at arbitrary irradiance and temperature are compared, and the simulation model that yields lowest root mean square error and the most accurate estimation of power temperature coefficient is identified. The simulated I-V curves using this model and the experimentally measured I-V curves on a flash tester at different temperatures and irradiances are provided as an input to all of the STC correction procedures. The average percentage errors in correction of maximum power (P max ), open-circuit voltage (V oc ), short-circuit current (I sc ),and fill factor (FF) were determined as a function of irradiance and temperature during measurement. Systematic biases introduced during correction by certain procedures were also identified. Based on the error estimation, constraints of various procedures, and requirements of high-throughput field I-V measurements, the most optimal STC correction procedure was identified. Moreover, the analysis of the root cause of superior performance of this procedure is also presented.

Abstract-Silicon-nitride trap layer stoichiometry in charge trap flash (CTF) memory strongly impacts electron and hole trap properties, memory performance, and reliability. Important tradeoffs between program/erase (P/E) levels (memory window), P-and E-state retention loss, and E-state window closure during cycling are shown. Increasing the Si richness of the SiN layer improves memory window, cycling endurance, and E-state retention loss but at the cost of higher P-state retention loss. The choice of SiN stoichiometry to optimize CTF memory performance and reliability is discussed.Index Terms-Charge trap flash (CTF), cycling endurance, program/erase (P/E) window, retention, SANOS, silicon nitride (SiN), SONOS.

No abstract

The All India Survey of Photovoltaic Module Reliability 2014 is an enhanced version of the survey conducted in the previous year, with detailed characterization of PV modules including current-voltage, infrared and electroluminescence imaging, visual inspection, insulation resistance test and interconnect breakage test. More than a thousand modules were inspected in the field and the main results of the survey are presented in this paper. The average P max degradation rate for the so-called 'good' modules (Group X) is 1.33%/year which is higher than that commonly projected by manufacturers, and widely employed in financial calculations. Modules falling in the 'not-so-good' category (Group Y) show even higher degradation rates, and it is at least partly due to higher number of micro-cracks in the modules, and increased degradation of the packaging materials like encapsulant, backsheet, etc. Modules in 'Hot' climates degrade faster than modules in the 'Non-Hot' climates. Degradation in fill factor is the primary cause for performance degradation in the young modules (ages <5 years), whereas short-circuit current degradation is the main contributor to power degradation in the older modules. Small installations (<100 kW p capacity) show higher degradation than large systems, which may be partly due to lack of proper due diligence by the owner at the time of procurement and installation.

25% annual PV growth is possible over the next decade

No abstract

Abstract-The influence of channel length and oxide thickness on the hot-carrier induced interface () and oxide ( ) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate and profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The and profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process.Index Terms-Channel length and oxide thickness dependence, charge pumping, hot-carrier effect, MOSFET, spatial profiling of damage.