Device scaling effects on hot-carrier induced interface and oxide-trapped charge distributions in MOSFETs

Abstract

Abstract-The influence of channel length and oxide thickness on the hot-carrier induced interface () and oxide ( ) trap profiles is studied in n-channel LDD MOSFET's using a novel charge pumping (CP) technique. The technique directly provides separate and profiles without using simulation, iteration or neutralization, and has better immunity from measurement noise by avoiding numerical differentiation of data. The and profiles obtained under a variety of stress conditions show well-defined trends with the variation in device dimensions. The generation has been found to be the dominant damage mode for devices having thinner oxides and shorter channel lengths. Both the peak and spread of the profiles have been found to affect the transconductance degradation, observed over different channel lengths and oxide thicknesses. Results are presented which provide useful insight into the effect of device scaling on the hot-carrier degradation process.Index Terms-Channel length and oxide thickness dependence, charge pumping, hot-carrier effect, MOSFET, spatial profiling of damage.

On the generation and recovery of interface traps in MOSFETs subjected to NBTI, FN, and HCI stress

“…Determination of ∆N IT is difficult due to the nonuniform localized nature of HCI damage. Although it is possible to determine the spatial profile of HCI damage [11], [23], it is outside the scope of this work. Therefore, FN degradation is expressed in terms of ∆N IT , whereas HCI degradation is expressed in terms of ∆I CP .…”

“…To verify whether HCI results can be explained by 2-D R-D model, process, device, and full band Monte Carlo simulations were performed using well-calibrated DIOS, DESSIS [41], and SMC [42] sim- ulators. Note that for the devices used in this study, CP measurement probes the drain half of the channel, from the center up to a fractional length (L F ) of about 0.4 [11], [23]. Therefore, HE and HH density distributions up to L F = 0.4 should be used to interpret the experimental results.…”

Analysis of the threshold voltage turn-around effect in high-voltage n-MOSFETs due to hot-carrier stress

“…3 demonstrates that first V th decreases due to hole trapping in the oxide bulk while after 10ks V th increases due to trapping of electrons by interface traps. To check these speculations, the CP technique with varying amplitude of the gate pulse [16,17] has been employed to investigate the N it (x) and N ot (x) distributions.…”

Hot carrier degradation improvement on submicron NMOSFET in Bipolar-CMOS-DMOS (BCD) process

“…It is well known that HC degradation can be improved by various methods [1][2][3]: minimize electric field in drain side Emax; separate the main current path away from maximum electrical field; push impact ionization region deep into silicon. The most widely used MOSFET device structure for improvement of hot carrier degradation is the lightly doped drain (LDD) MOSFET.…”