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Values of the aspect ratio for trenches etched into HgCdTe by an electron cyclotron resonance (ECR) plasma containing hydrogen and argon are limited by the phenomenon of etch lag. Modeling this plasma as an ion assisted, reactiveetching process leads to a set of conditions that greatly reduces etch lag. Use of these new process conditions produces trenches with aspect ratios greater than 3, widths less than 3 m, and depths in excess of 15 m.

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The erosion rate of resist during electron cyclotron resonance (ECR) plasma etching of II-VI semiconductors is the limiting factor for the selectivity (values range from 5:1 to 10:1). We have measured the erosion rates of AZ 1529, a commercially available diazonaphthoquinone (DNQ) novolak photoresist, under plasma conditions optimized for etching of the underlying semiconductor and have developed an in-situ technique to "harden" the resist by exposing it to an argon-only ECR plasma. A subsequent standard plasma process can then be used to etch the II-VI material, thereby achieving selectivity values greater than 50:1.

We have developed a low temperature procedure for molecular beam epitaxy of CdTe buffer layers on {211} Si wafers and have used Si/ZnTe/CdTe composite substrates for molecular beam epitaxy of double layer Hg1−xCdxTe heterostructures. Planar p-on-n double layer heterostructures were formed by an implantation technique and test diodes were fabricated and characterized. At 77 K, devices with 30×30 μm2 junction area had R0A values in the range 1.5×106–1×107Ω cm2 with a uniform cut-off wavelength of 4.65 μm.

In the past several years, we have made significant progress in the growth of CdTe buffer layers on Si wafers using molecular beam epitaxy (MBE) as well as the growth of HgCdTe onto this substrate as an alternative to the growth of HgCdTe on bulk CdZnTe wafers. These developments have focused primarily on mid-wavelength infrared (MWIR) HgCdTe and have led to successful demonstrations of high-performance 1024 ϫ 1024 focal plane arrays (FPAs) using Rockwell Scientific's double-layer planar heterostructure (DLPH) architecture. We are currently attempting to extend the HgCdTe-on-Si technology to the long wavelength infrared (LWIR) and very long wavelength infrared (VLWIR) regimes. This is made difficult because the large lattice-parameter mismatch between Si and CdTe/HgCdTe results in a high density of threading dislocations (typically, Ͼ5E6 cm Ϫ2 ), and these dislocations act as conductive pathways for tunneling currents that reduce the R o A and increase the dark current of the diodes. To assess the current state of the LWIR art, we fabricated a set of test diodes from LWIR HgCdTe grown on Si. Silicon wafers with either CdTe or CdSeTe buffer layers were used. Test results at both 78 K and 40 K are presented and discussed in terms of threading dislocation density. Diode characteristics are compared with LWIR HgCdTe grown on bulk CdZnTe.

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