No abstract

No abstract

The design and integration of an RF front-end for WCDMA applications using an above-IC BAW band-pass filter is reported in this paper. SoC integration will become easier to achieve using the proposed above-IC approach. The use of a BAW filter between the LNA and the mixer permits also to relax linearity constraints and thus, power consumption for the down-conversion mixers. This first experimental chip is designed and fabricated in a 0.25µm SiGe:C BiCMOS process enhanced with above-IC capabilities. The BAW filter is fabricated by CEA-LETI and CSEM. The above-IC BAW process is plugged over the BiCMOS final passivation layer, and the electrical contact with the rest of the circuit is realized at the last IC metal layer. This circuit uses film bulk acoustic resonators (FBAR). The piezoelectric efficiency of the AlN layer is confirmed by RF characterization of stand-alone resonators, presenting a coupling coefficient k t 2 of 6.3% and a Qfactor around 900 [1].One of the major issues of FDD x-CDMA standards is the fullduplex mode operation of the receive and transmit sections. This leads to very stringent requirements on the receiver in order to meet the desired sensitivity (-107dBm) while coping with the strong out-of-band -23dBm TX leakage [2]. In terms of system specifications, the noise factor, the conversion gain and also the out-of-band 2 nd -and 3 rd -order linearity are the major parameters to be taken into account for a thriving WCDMA receiver.Up-to-date SiGe:C BiCMOS processes offer active and passive devices to meet all linearity and noise specifications of 3G at low power consumption. Within this technology frame, the zero-IF architecture is a system implementation that permits to fulfill the WCDMA standard with a very high level of integration. The proposed circuit is a simplified implementation of a zero-IF frontend to evaluate all the major features ( Fig. 21.3.1). From the system point of view, the input LNA has to be a single-ended circuit, connected directly to the single RX path of a duplexer. It is followed by an on-chip balun, with medium insertion losses, allowing a high level of integration. In order to cope with the large unwanted Tx signal and to relax the down-conversion mixer 2 nd order non-linearity constraints, system specifications impose the use of a narrow-band RF band-pass filter at 2.14GHz. The filter mask is depicted in Fig. 21.3.2. Simulations of such RF band-pass filters implemented with BAW resonators predict better out-ofband rejection than the existent data on SAW filters. This leads to a mixer specification with reduced linearity performance with respect to a classical zero-IF RX path, thus, lowering its power consumption. Moreover, the SoC approach avoids parasitics from ESD diodes and magnetic coupling from wire-bonding, thus, lowering the total noise factor. In addition, this also allows a large choice of matching impedances.The single-ended LNA is based on a cascode topology with degeneration emitter inductor in order to get the best trade-off between 50Ω matching and noise...

No abstract

International audienceA 60 GHz cavity-backed antenna array integrated on high-resistivity silicon is demonstrated. The antenna design makes use of Through-Silicon-Vias (TSV), silicon micromachining, and wafer-to-wafer bonding to meet the bandwidth and radiation gain requirements for short-range multi-Gbps communications. The fabrication process is presented. Simulated and experimental results show that the antenna element covers easily the 57–66 GHz standard band with good impedance matching and more than 5 dBi of gain. Several fixed-beam four-element antenna arrays demonstrate the capabilities for beam-steering across a range up to ±60°