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The growth of AlGaN∕GaN heterostructure on Si (001) substrates by molecular-beam epitaxy using ammonia as nitrogen precursor is reported. The structural, optical, and electrical properties of such heterostructures are assessed. It is shown that a two-dimensional electron gas is formed at the Al0.23Ga0.77N∕GaN interface. This type of heterostructure exhibits a sheet carrier density of 4.2×1012cm−2 with a mobility of 730cm2∕Vs at room temperature. Preliminary results concerning high-electron-mobility-transistor static characteristics are presented.

International audienceA 60 GHz cavity-backed antenna array integrated on high-resistivity silicon is demonstrated. The antenna design makes use of Through-Silicon-Vias (TSV), silicon micromachining, and wafer-to-wafer bonding to meet the bandwidth and radiation gain requirements for short-range multi-Gbps communications. The fabrication process is presented. Simulated and experimental results show that the antenna element covers easily the 57–66 GHz standard band with good impedance matching and more than 5 dBi of gain. Several fixed-beam four-element antenna arrays demonstrate the capabilities for beam-steering across a range up to ±60°

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We report on the growth of wurtzite-GaN layers by molecular beam epitaxy using ammonia on Si(100) substrates. We show that using 4° misoriented Si(100) substrates, GaN layers are obtained with a dominant orientation. The nucleation conditions of the AlN buffer layer as well as the entire growth process are described and compared with the process developed for the growth on Si(111) substrates, already well optimised in our laboratory [1]. The crystalline quality and polarity are assessed by transmission electron microscopy, X-ray diffraction and chemical etching. The most noticeable features of the layers grown are the high crystal quality of the AlN/Si interface, the Ga-polarity of the final GaN layer and especially the presence of the wurtzite phase only.1 Introduction GaN-based devices such as Light Emitting Diodes (LED), High Electron Mobility Transistors (HEMTs) are usually grown on sapphire (Al 2 0 3 ) or silicon carbide (SiC) substrates. Nevertheless, the growth of device-quality GaN-based heterostructures on silicon substrates is of huge interest in terms of cost, availability, processing and integration. Hexagonal GaN has been already successfully deposited on Si(111) substrates either by metalorganic chemical vapor deposition (MOCVD) or by molecular beam epitaxy (MBE) methods, in spite of the difficulties related to the very high reactivity of the silicon surface with nitrogen, the large lattice mismatch (-16.2%) and the large difference in thermal expansion coefficient (113%). However, from the point of view of integrating GaN devices with silicon technology, the Si(100) substrate is preferred because it is the most widely used in silicon mainstream technology. Contrary to the (111) plane, the (100) silicon plane does not present a 6-fold symmetry but a 4-fold symmetry more suitable for the epitaxial growth of a cubic phase. Nevertheless, the (β-GaN) cubic phase is metastable, and the thermodynamically stable hexagonal GaN phase could be grown on the (100) plane. In addition to the square surface symmetry, the Si(100) nominal surface exhibits a 2x1 surface reconstruction with two types of domains rotated by 90°. Silicon atoms have dangling bonds which forms dimers in the [110] direction for one domain and in the [1][2][3][4][5][6][7][8][9][10] for the other domain. Adjacent domains are separated by a monoatomic step (a 0 /4) and have respectively 2x1 and 1x2 surface reconstruction. It has been shown that the presence of monoatomic steps leads to the formation of antiphase boundaries domains in GaAs grown on Si(100) (APBs)[2] and a two-domains structure rotated by 30° when growing 2H-AlN [3]. To obtain a silicon (100) surface with only one domain, single atomics steps must be annihilated or double atomics steps (a 0 /2) must be formed using, for example, a (100) vicinal plane [4]. Indeed,

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First part of this paper discusses decoupling method limitation within the Power Delivery Network of a classical circuit and challenges introduced by 3D integrated circuit in term of power management. Solutions are exposed, such as integration of decoupling capacitor on silicon interposer.Second part of the paper focuses on the Through Silicon Capacitor (or TSC) as an alternative decoupling solution cointegrated with Through Silicon Vias on silicon interposer. TSC realization is described and architectural benefits of adding a partial copper-filling prior to the Metal-InsulatorMetal stack deposition are discussed.A distributed analytical model is used to quantify partial filling resistance contribution, pointing out a 6 decade decrease in ESR value of the structure. TSC process and matrix design parameters impact on capacitance density are studied. Finally, electrical performances of TSC modules are evaluated showing a low intrinsic impedance behavior granted by TSC parallel structure.

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