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Using a quasichemical approach, the total native defect concentration and the minimum deviation in stoichiometry have been calculated in CdTe crystals as a function of the Cd pressure at various temperatures. With this knowledge, CdTe and (Cd,Zn)Te wafers have been subjected to postgrowth step annealing treatment under conditions such that the crystals are in equilibrium with a Cd or (Cd,Zn) vapor corresponding to the minimum in deviation from stoichiometry at each annealing temperature. The step annealed CdTe and (Cd,Zn)Te wafers have been examined under infrared microscopy and have shown significant reduction in the concentration of Te precipitates, whereas the unannealed wafers have had numerous Te precipitates distributed throughout the bulk. HgCdTe epitaxial films have been grown on the step annealed CdTe and (Cd,Zn)Te wafers as well as on unannealed wafers from the same boule. Examination of the cross sections of the epitaxial films indicates appearance of Te precipitates in films grown on unannealed substrates, whereas no Te precipitation was evident in films grown on the annealed substrates leading to the inference that the occurrence of Te precipitates in the (Hg,Cd)Te films is possibly related to the presence of Te precipitates in the substrates. Thermal migration of Te under a temperature gradient during step annealing is suggested as a possible mechanism in the elimination of larger size Te precipitates whereas the extremely fine precipitates (<1 μm) appear to need in-diffusion of metal vapor for their elimination.

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It has been reported that the basic electrical properties of n-type long wave length infrared (LWIR) HgCdTe grown on silicon, including the majority carrier mobility (l e ) and minority carrier lifetime (s), are qualitatively comparable to those reported for LWIR HgCdTe grown on bulk CdZnTe by molecular beam epitaxy (MBE). Detailed measurements of the majority carrier mobility have revealed important differences between the values measured for HgCdTe grown on bulk CdZnTe and those measured for HgCdTe grown on buffered silicon substrates. The mobility of LWIR HgCdTe grown on buffered silicon by MBE is reported over a large temperature range and is analyzed in terms of standard electron scattering mechanisms. The role of dislocation scattering is addressed for high dislocation density HgCdTe grown on lattice-mismatched silicon. Differences between the low temperature mobility data of HgCdTe grown on bulk CdZnTe and HgCdTe grown on silicon are partially explained in terms of the dislocation scattering contribution to the total mobility.

We have initiated a joint effort to better elucidate the fundamental mechanisms underlying As-doping in molecular beam epitaxy (MBE)-grown HgCdTe. We have greatly increased the As incorporation rate by using an As cracker cell. With a cracker temperature of 700°C, As incorporation as high as 4 ϫ 10 20 cm Ϫ3 has been achieved by using an As-reservoir temperature of only 175°C. This allows the growth of highly doped layers with high quality as measured by low dislocation density. Annealing experiments show higher As-activation efficiency with higher anneal temperatures for longer time and higher Hg overpressures. Data are presented for layers with a wide range of doping levels and for layer composition from 0.2 to 0.6.

Multiple polycrystalline CdS/CdTe solar cells with efficiencies greater than 15% were produced on buffered, commercially-available Pilkington TEC Glass TM at EPIR Technologies, Inc. (EPIR) and verified by the National Renewable Energy Laboratory (NREL). n-CdS and p-CdTe were grown by chemical bath deposition (CBD) and close space sublimation, respectively. Samples with sputter-deposited CdS were also investigated. Initial results indicate that this is a viable dry-process alternative to CBD for production-scale processing. Published results for polycrystalline CdS/CdTe solar cells with high efficiencies are typically based upon cells utilizing research-grade transparent conducting oxides (TCOs) requiring high-temperature processing inconducive to low-cost manufacturing. EPIR's results for cells on commercial glass were obtained by implementing a high resistivity SnO 2 buffer layer and optimizing the CdS window layer thickness. The high resistivity buffer layer prevents the formation of CdTe-TCO junctions, thereby maintaining a high open circuit voltage and fill factor; while using a thin CdS layer reduces absorption losses and improves the short circuit current density. EPIR's best device demonstrated an NREL-verified efficiency of 15.3%. The mean efficiency of hundreds of cells produced with a buffer layer between December 2010 and June 2011 is 14.4%. Quantum efficiency results are presented to demonstrate EPIR's progress toward NREL's best-published results.

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