Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

Die-attach bonding was evaluated using a transient liquid phase (TLP) bonding method on a Cu/In, Au/In and Cu-Sn3Ag metal stack. TLP bonding is a relatively low cost process since thin layers of material are used and, at the same time, has higher reliability due to the good thermal resistance of the intermetallic compounds (IMCs) formed. The bonded samples were aged at 300°C for 500 h and thermal cycled from −40°C to 125°C for 500 cycles. The results showed that the shear strength of the Cu/In joint was higher than that of the Au/In joint with increasing aging time. Cu/In specimens on a ceramic substrate also showed good reliability results during the thermal cycling test. Even though Cu/In TLP bonding is not popular in conventional electronics, it is suitable for high temperature electronics due to the simplicity of the IMC formation.

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