Flip Chip Packaging of Digital Silicon Photonics MEMS Switch for Cloud Computing and Data Centre

Yuan, Hwang How; Lee, Jun Su; Seok, Tae Joon; Forencich, Alex; Grant, Hannah R.; Knutson, Dylan; Quack, Niels; Han, Sangyoon; Muller, R.S.; Papen, George C.; Wu, M.C.; O’Brien, Peter

doi:10.1109/jphot.2017.2704097

Cited by 21 publications

(9 citation statements)

References 31 publications

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“…For the small Si caps, the theoretical cap deflection is on the order of a few nanometers (calculated according to equation (1) in section III.C), which is below the detection limit of our measurement setup, thus the sealing yield of small cavities cannot be confirmed by this method. The protrusion of the transferred Si caps out of the cavity wafer plane were within 31 ± 1 µm, which is below typical solder and stud bump heights of ∼50 µm after flip chip bonding [47]. Thus, our approach is dimensionally compatible with flip chip bonding as illustrated in Fig.…”

Section: A Yield Of Thin Cap Transfer and Sealingmentioning

confidence: 72%

Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages

Wang

Bleiker

Edinger

et al. 2019

J. Microelectromech. Syst.

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Vacuum and hermetic packaging is a critical requirement for optimal performance of many micro-electromechanical systems (MEMS), vacuum electronics, and quantum devices. However, existing packaging solutions are either elaborate to implement or rely on bulky caps and footprint-consuming seals. Here, we address this problem by demonstrating a waferlevel vacuum packaging method featuring transfer bonding of 25-µm-thin silicon (Si) caps that are transferred from a 100-mm-diameter silicon-on-insulator (SOI) wafer to a cavity wafer to seal the cavities by gold-aluminum (Au-Al) thermocompression bonding at a low temperature of 250 • C. The resulting wafer-scale sealing yields after wafer dicing are 98% and 100% with sealing rings as narrow as 6 and 9 µm, respectively. Despite the small sealing footprint, the Si caps with 9-µm-wide sealing rings demonstrate a high mean shear strength of 127 MPa. The vacuum levels in the getter-free sealed cavities are measured by residual gas analysis to be as low as 1.3 mbar, based on which a leak rate smaller than 2.8 × 10 −14 mbarL/s is derived. We also show that the thickness of the Si caps can be reduced to 6 µm by post-transfer etching while still maintaining excellent hermeticity. The demonstrated ultra-thin packages can potentially be placed in between the solder bumps in flip-chip interfaces, thereby avoiding the need of through-capvias in conventional MEMS packages. [2018-0257] Index Terms-Vacuum, hermetic, packaging, sealing, MEMS, ultra-thin package, small footprint, transfer bonding, 3D integration, flip chip, aluminum, gold, thermo-compression bonding. I. INTRODUCTION V ACUUM packaging is a process for encapsulating a device (e.g. a MEMS or nano-electro-mechanical system (NEMS) device) in a vacuum environment and maintaining the internal vacuum level using hermetic seals. It enables functionality and long-term reliability of various MEMS devices, such as inertial sensors, pressure sensors and infrared detectors, but typically also constitutes a significant part of their cost in high-volume production [1], [2]. As a general trend,

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Section: A Yield Of Thin Cap Transfer and Sealingmentioning

confidence: 72%

Wafer-Level Vacuum Sealing by Transfer Bonding of Silicon Caps for Small Footprint and Ultra-Thin MEMS Packages

Wang

Bleiker

Edinger

et al. 2019

J. Microelectromech. Syst.

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“…Large-scale circuits further require a large number of photonic input and output ports, as well as a large number of electrical interfaces for both low-frequency (<10 MHz) for MEMS actuation, as well as for high-speed (>50 GHz) modulators and photodetectors. Current integration efforts are addressing these challenges [37]. The voltage levels required in demonstrated Silicon Photonic MEMS devices are typically several 10s of volts.…”

Section: Towards Integrated Circuitsmentioning

confidence: 99%

MEMS-Enabled Silicon Photonic Integrated Devices and Circuits

Quack

Sattari

Takabayashi

et al. 2020

IEEE J. Quantum Electron.

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Photonic integrated circuits have seen a dramatic increase in complexity over the past decades. This development has been spurred by recent applications in datacenter communications and enabled by the availability of standardized mature technology platforms. Mechanical movement of wave-guiding structures at the micro-and nanoscale provides unique opportunities to further enhance functionality and to reduce power consumption in photonic integrated circuits. We here demonstrate integration of MEMS-enabled components in a simplified silicon photonics process based on IMEC's Standard iSiPP50G Silicon Photonics Platform and a custom release process.

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“…The hundreds or even thousands of actuators and monitors require connections between the photonics and the electronics, which, if the electronics is not integrated on the same chip, translates into a packaging and assembly challenge. 47 Add to that the constraints of hermetically sealing the MEMS actuators, the interfacing with several (tens of) optical fibers, as well as high-speed RF input and output signal, and it becomes clear that packaging cannot be treated as an afterthought in programmable photonics.…”

Section: Packaging Drivers and Interfacesmentioning

confidence: 99%