Over the last 20 years, silicon photonics has revolutionized the field of integrated optics, providing a novel and powerful platform to build mass-producible optical circuits. One of the most attractive aspects of silicon photonics is its ability to provide extremely small optical components, whose typical dimensions are an order of magnitude smaller than those of optical fiber devices. This dimension difference makes the design of fiberto-chip interfaces challenging and, over the years, has stimulated considerable technical and research efforts in the field. Fiber-to-silicon photonic chip interfaces can be broadly divided into two principle categories: in-plane and out-of-plane couplers. Devices falling into the first category typically offer relatively high coupling efficiency, broad coupling bandwidth (in wavelength), and low polarization dependence but require relatively complex fabrication and assembly procedures that are not directly compatible with wafer-scale testing. Conversely, out-of-plane coupling devices offer lower efficiency, narrower bandwidth, and are usually polarization dependent. However, they are often more compatible with high-volume fabrication and packaging processes and allow for on-wafer access to any part of the optical circuit. In this paper, we review the current state-of-the-art of optical couplers for photonic integrated circuits, aiming to give to the reader a comprehensive and broad view of the field, identifying advantages and disadvantages of each solution. As fiber-to-chip couplers are inherently related to packaging technologies and the co-design of optical packages has become essential, we also review the main solutions currently used to package and assemble optical fibers with silicon-photonic integrated circuits.

Direct-gap gain up to 850 cm(-1) at 0.74 eV is measured and modeled in optically pumped Ge-on-Si layers for photoexcited carrier densities of 2.0 × 10(20) cm(-3). The gain spectra are correlated to carrier density via plasma-frequency determinations from reflection spectra. Despite significant gain, optical amplification cannot take place, because the carriers also generate pump-induced absorption of ≈7000 cm(-1). Parallel studies of III-V direct-gap InGaAs layers validate our spectroscopy and modeling. Our self-consistent results contradict current explanations of lasing in Ge-on-Si cavities.

Dedicated multi-project wafer (MPW) runs for photonic integrated circuits (PICs) from Si foundries mean that researchers and small-to-medium enterprises (SMEs) can now afford to design and fabricate Si photonic chips. While these bare Si-PICs are adequate for testing new device and circuit designs on a probe-station, they cannot be developed into prototype devices, or tested outside of the laboratory, without first packaging them into a durable module. Photonic packaging of PICs is significantly more challenging, and currently orders of magnitude more expensive, than electronic packaging, because it calls for robust micron-level alignment of optical components, precise real-time temperature control, and often a high degree of vertical and horizontal electrical integration. Photonic packaging is perhaps the most significant bottleneck in the development of commercially relevant integrated photonic devices. This article describes how the key optical, electrical, and thermal requirements of Si-PIC packaging can be met, and what further progress is needed before industrial scale-up can be achieved.

We present a theoretical optimisation of 1D apodized grating couplers in a "pure" Silicon-On-Insulator (SOI) architecture, i.e. without any bottom reflector element, by means of a general mutative method. We perform a comprehensive 2D Finite Difference Time Domain study of chirped and apodized grating couplers in 220 nm SOI, and demonstrate that the global maximum coupling efficiency in that platform is capped to 65% (-1.9 dB). Moving to designs with thicker Si-layers, we identify a new record design in 340 nm SOI, with a simulated coupling efficiency of 89% (-0.5 dB). Going to thicker Si layers does not further improve the efficiency, implying that -0.5 dB may be a global maximum for a grating coupler in SOI without a bottom-reflector. Even after allowing for 193 nm UV-lithographic fabrication constraints, the 340 nm design still offers -0.7 dB efficiency. These new apodized designs are the first pure SOI couplers compatible with deep-UV lithography to offer better than -1 dB insertion losses. With only very minor changes to existing deposition and lithography recipes, they are compatible with the multi-project wafer runs already offered by Si-Photonics foundries.

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