Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing intersymbol interference (ISI) in high-speed chip-to-chip communication. A loopunrolled approach is widely used in work toward the design of high-speed multitap DFEs. It eliminates the feedback operation in first post-cursor equalization [1][2][3], an operation that limits operational speed in conventional multi-tap DFEs. There are two problems, however, to its application to equalization of 16Gb/s signals. The first is that additional components in the feedback path, used for speculation on the basis of sampled data, increase 2 nd -tap feedback delay, preventing high-speed operations. The second problem is that jitter increase in equalized waveforms prevents accurate clock timing recovery because the 1 st tap ISI of the waveform is left un-equalized. In response to this situation, we have developed three techniques for achieving 16Gb/s communication: (1) an analog feedforward technique for high-speed 1 st -tap ISI equalization, (2) an analog feedforward technique for jitter reduction in equalized edges, and (3) technique for employing bypass feedback and a voltage swing limiter in order to speed-up both 2 ndtap and 3 rd -tap equalization. We have applied these techniques to a 16Gb/s equalizer fabricated in a 90nm CMOS process, and their use helps achieve a 33% increase in operating speed over that with conventional multi-tap DFEs [3].
This paper investigates the twisted differential transmission line structure to achieve high-speed signal transmission and electromagnetic interference (EMI) noise reduction of global interconnects in Si LSIs. The differential transmission line in Si LSIs can transmit a 12 Gbps pulse signal and has the capability of reducing EMI noise. The proposed twisted-diagonal-pair line provides high-speed, low-EMI-noise, high-crosstalk-robustness and high-density global interconnects in Si LSIs.
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