Twisted Differential Transmission Line Structure for Global Interconnect in Si LSI

Ito, Hiroyuki; Gomi, S.; Sugita, Hideyuki; Okada, Kei; Masu, Kazuya

doi:10.1143/jjap.44.2774

Cited by 5 publications

(4 citation statements)

References 6 publications

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“…Ito et al proposed a twisted differential transmission lines with four metal wires [20] as shown in Figure 12. The stacked wires are twisted in the stretching direction and, thus, in the direction of the currents.…”

Section: Crossed Bundlingmentioning

confidence: 99%

A Novel MEMS Respiratory Flow Sensor

2010

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Our experience in the design of an ultra-high speed image sensor targeting the theoretical maximum frame rate is summarized. The imager is the backside illuminated in situ storage image sensor (BSI ISIS). It is confirmed that the critical factor limiting the highest frame rate is the signal electron transit time from the generation layer at the back side of each pixel to the input gate to the in situ storage area on the front side. The theoretical maximum frame rate is estimated at 100 Mega-frames per second (Mfps) by transient simulation study. The sensor has a spatial resolution of 140,800 pixels with 126 linear storage elements installed in each pixel. The very high sensitivity is ensured by application of backside illumination technology and cooling. The ultra-high frame rate is achieved by the in situ storage image sensor (ISIS) structure on the front side. In this paper, we summarize technologies developed to achieve the theoretical maximum frame rate, including: (1) a special p-well design by triple injections to generate a smooth electric field backside towards the collection gate on the front side, resulting in much shorter electron transit time; (2) design technique to reduce RC delay by employing an extra metal layer exclusively to electrodes responsible for ultra-high speed image capturing; (3) a CCD specific complementary on-chip inductance minimization technique with a couple of stacked differential bus lines.

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Section: Crossed Bundlingmentioning

confidence: 99%

A Novel MEMS Respiratory Flow Sensor

2010

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“…For the co-planar line structure, the line pitch has to be large to have enough crosstalk robustness. For the diagonal-pair line structure, the line pitch can be reduced because a common-mode noise can be cancelled [2]. The line space between differential pairs is determined to have less than 0.05 of the crosstalk coefficient.…”

Section: Estimation Of Single Interconnectmentioning

confidence: 99%

“…A long interconnect is usually divided by several repeaters to reduce delay time. On-chip transmission line structure for global interconnect has been proposed [1,2]. Transmission line can propagate signal faster than RC line.…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Evaluation of on-chip transmission line interconnect using wire length distribution

Inoue

Ito

Gomi

et al. 2005

Proceedings of the 2005 Conference on Asia South Pacific Design Automation - ASP-DAC '05

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On-chip transmission-line interconnect has been proposed to reduce delay time and power consumption. The transmission line is used to replace long RC interconnects. This paper proposes the methodology to replace RC lines with transmission lines, which are estimated with Wire Length Distribution (WLD). Advantages of on-chip transmission line are discussed from the view point of delay time and power consumption.

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