An on-chip transmission-line interconnect has been proposed to reduce the delay time and power consumption. Transmission lines are used to replace long RC interconnects, and can greatly improve circuit performance. In this work, we estimate the performance of circuits using on-chip transmission line technologies, focusing on delay improvement. A derivation algorithm for the wire length of each path in a circuit is proposed. In simulated results, replacement with an on-chip transmission line can improve the critical-path delay by 10%.