On-chip transmission line for long global interconnects

Ito, Hiroyuki; Inoue, Junpei; Gomi, S.; Sugita, Hideyuki; Okada, Kei; Masu, Kazuya

doi:10.1109/iedm.2004.1419258

Cited by 32 publications

(16 citation statements)

References 3 publications

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“…In [7] and [8], Ito et al propose to use differential TLine for global layer transmission, and reported measured 8 Gbps data rate under 180 nm technology. Hashimoto et al further investigate the performance limitation of T-Lines under present and future technologies.…”

Section: Previous Workmentioning

confidence: 98%

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Zhu

Shi

Cheng

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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We extend the Surfliner on-chip distortionless transmission line scheme and provide more details for the implementation issues. Surfliner seeks to approach distortionless transmission by intentionally adding shunt resistors between the signal line and the ground. In theory if we distributively make the shunt conductance G=RC/L, there will be no distortion at the receiver end and the signal propagates at the speed of light. We show the feasibility and advantages of this shunt resistor scheme by a real design case of single-ended microstrip line in 0.10µm technology. The simulation results indicate we can achieve near perfect signaling of 10 Gbps data over a 10 mm serial link, yet no pre-emphasis/equalization or other special techniques are needed. Guidelines for determining the optimal value and spacing of the shunt resistors are also provided.

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Section: Previous Workmentioning

confidence: 98%

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Zhu

Shi

Cheng

et al. 2007

2007 Asia and South Pacific Design Automation Conference

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“…The key specs of our baseline bus are summarized in Table 1. While more detailed analyses of the link design and implementation could be helpful, they are beyond the scope of this paper and have been dealt with in some prior works [26,27,32,39] . We have also taped out a test chip (Figure 1) to further validate the circuit parameters obtained from our circuit simulations.…”

Section: Basic Transmission Line-based Busmentioning

confidence: 99%

Enhancing effective throughput for transmission line-based bus

Carpenter

Hu$^{

Kocabas

et al. 2012

2012 39th Annual International Symposium on Computer Architecture (ISCA)

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Main-stream general-purpose microprocessors require a collection of high-performance interconnects to supply the necessary data movement. The trend of continued increase in core count has prompted designs of packet-switched network as a scalable solution for future-generation chips. However, the cost of scalability can be significant and especially hard to justify for smaller-scale chips. In contrast, a circuit-switched bus using transmission lines and corresponding circuits offers lower latencies and much lower energy costs for smaller-scale chips, making it a better choice than a full-blown network-on-chip (NoC) architecture. However, shared-medium designs are perceived as only a niche solution for small-to medium-scale chips.In this paper, we show that there are many low-cost mechanisms to enhance the effective throughput of a bus architecture. When a handful of highly cost-effective techniques are applied, the performance advantage of even the most idealistically configured NoCs becomes vanishingly small. We find transmission line-based buses to be a more compelling interconnect even for large-scale chipmultiprocessors, and thus bring into doubt the centrality of packet switching in future on-chip interconnect.

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“…For the application of transmission lines as global interconnect in CMOS circuits, electromagnetic (full-wave and quasi-TEM) analyses of on-chip transmission lines on silicon substrate (e.g., [18], [20], [26], [27], [29]) provided the groundwork. Circuit-level studies (e.g., [16], [17], [21], [34]) have been carried out to characterize the performance of transmission line based onchip interconnect. Novel signaling and modulation schemes have been proposed [14], [25].…”

Section: Background and Related Workmentioning

confidence: 99%

A design space exploration of transmission-line links for on-chip interconnect

Carpenter¹,

Hu$^{²,

Huang³

et al. 2011

IEEE/ACM International Symposium on Low Power Electronics and Design

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Abstract-With increasing core count, chip multiprocessors (CMP) require a high-performance interconnect fabric that is energy-efficient. Well-engineered transmission linebased communication systems offer an attractive solution, especially for CMPs with a moderate number of cores. While transmission lines have been used in a wide variety of purposes, there lack comprehensive studies to guide architects to navigate the circuit and physical design space to make proper architecture-level analyses and tradeoffs. This paper makes a first-step effort in exploring part of the design space. Using detailed simulation-based analysis, we show that a shared-medium fabric based on transmission line can offer better performance and a much better energy profile than a conventional mesh interconnect.

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On-chip transmission line for long global interconnects

Cited by 32 publications

References 3 publications

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Approaching Speed-of-light Distortionless Communication for On-chip Interconnect

Enhancing effective throughput for transmission line-based bus

A design space exploration of transmission-line links for on-chip interconnect

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