We devise a central triangular sequence to minimize the escape routing layers in area array packaging. We use a network flow model to analyze the bottleneck of the routable pins. The triangular patterns are generated in a reverse order from the last to the first layer. We demonstrate that the triangular pin sequence maximizes the sum of escape pins in the accumulated layers and thus minimize the number of escape routing layers. A test case is presented to illustrate the approach.
We extend the Surfliner on-chip distortionless transmission line scheme and provide more details for the implementation issues. Surfliner seeks to approach distortionless transmission by intentionally adding shunt resistors between the signal line and the ground. In theory if we distributively make the shunt conductance G=RC/L, there will be no distortion at the receiver end and the signal propagates at the speed of light. We show the feasibility and advantages of this shunt resistor scheme by a real design case of single-ended microstrip line in 0.10µm technology. The simulation results indicate we can achieve near perfect signaling of 10 Gbps data over a 10 mm serial link, yet no pre-emphasis/equalization or other special techniques are needed. Guidelines for determining the optimal value and spacing of the shunt resistors are also provided.
Discovering unknown aspects of non-equilibrium systems with hidden strange attractors is an attractive research topic. A novel quadratic hyperjerk system is introduced in this paper. It is noteworthy that this non-equilibrium system can generate hidden chaotic attractors. The essential properties of such systems are investigated by means of equilibrium points, phase portrait, bifurcation diagram, and Lyapunov exponents. In addition, a fractional-order differential equation of this new system is presented. Moreover, an electronic circuit is also designed and implemented to verify the feasibility of the theoretical model.
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