Enhancing effective throughput for transmission line-based bus

Abstract

Main-stream general-purpose microprocessors require a collection of high-performance interconnects to supply the necessary data movement. The trend of continued increase in core count has prompted designs of packet-switched network as a scalable solution for future-generation chips. However, the cost of scalability can be significant and especially hard to justify for smaller-scale chips. In contrast, a circuit-switched bus using transmission lines and corresponding circuits offers lower latencies and much lower energy costs for smaller-scale chips, making it a better choice than a full-blown network-on-chip (NoC) architecture. However, shared-medium designs are perceived as only a niche solution for small-to medium-scale chips.In this paper, we show that there are many low-cost mechanisms to enhance the effective throughput of a bus architecture. When a handful of highly cost-effective techniques are applied, the performance advantage of even the most idealistically configured NoCs becomes vanishingly small. We find transmission line-based buses to be a more compelling interconnect even for large-scale chipmultiprocessors, and thus bring into doubt the centrality of packet switching in future on-chip interconnect.

WiSync

“…Transmission Lines (TLs). TLs can provide on-chip broadcast [4,5,10,33,34,41,43]. As a result, they have been used for synchronization.…”

“…Abellan et al [4,5] implement locks and barriers using TLs, as they broadcast signals over these TLs. Other designs use TLs for a variety of broadcast networks [10,34,43]. Nanophotonics.…”

“…Other Technologies. There are two emerging technologies that can also offer on-chip broadcast capabilities: transmission lines (TLs) [4,5,10,33,34,41,43] and nanophotonics [6,21,23,42,46,47]. While these technologies are more energy-efficient and provide more bandwidth than wireless communication, they are more complicated and less scalable than wireless communication.…”

Exploiting Transmission Lines on Heterogeneous Networks-on-Chip to Improve the Adaptivity and Efficiency of Cache Coherence

“…Utilization of TL: TL based globally shared on-chip interconnect [3,4,5,6] performs well compared to conventional packet-switched networks. Heterogeneous interconnects utilizing a multi-band TL bus [7,8] provide higher bandwidth.…”

“…Transmission line [4,5] is utilized as a latency-optimized interconnect and combined with the packet-switched network to create heterogeneous on-chip interconnects. Different type of messages are adaptively directed through the proper medium.…”