A Low-Latency and High-Power-Efficient On-Chip LVDS Transmission Line Interconnect for an RC Interconnect Alternative

Highly Energy-Efficient On-Chip Pulsed-Current-Mode Transmission Line Interconnect

“…This indicates that the delay characteristics of the proposed PTLIs are better than those of other on-chip interconnects. Energy per bit of our interconnects is almost the same as that reported in a previous study (Ito et al, 2008) and is greater than that reported in another study (Ito et al, 2007). The operating frequency in the previous study (Ito et al, 2007) is higher than that of the proposed PTLI.…”

“…Energy per bit of our interconnects is almost the same as that reported in a previous study (Ito et al, 2008) and is greater than that reported in another study (Ito et al, 2007). The operating frequency in the previous study (Ito et al, 2007) is higher than that of the proposed PTLI. However, the comparison of the power consumption at 8 Gb/s shows that the power consumption of PTLI is smaller than that in (Ito et al, 2007), as shown in Figure 20.…”

“…The operating frequency in the previous study (Ito et al, 2007) is higher than that of the proposed PTLI. However, the comparison of the power consumption at 8 Gb/s shows that the power consumption of PTLI is smaller than that in (Ito et al, 2007), as shown in Figure 20. Wiring area is one of the most significant characteristics of on-chip interconnects.…”

“…Maximum bit-rate comparable to that of TLIs can be achieved by using RC lines in a bundle; however, this would imply that the RC lines will occupy virtually the same area as the TLIs. The area per bit of the proposed point-to-point PTLI is almost equal to that of the other point-to-point TLIs Ito et al, 2005;Ishii et al, 2006;Ito et al, 2007Ito et al, , 2008Lee et al, 2004). The area per bit of the proposed multi-drop PTLI is the equal to the bidirectional and multi-drop transmission line interconnects (Ito et al, 2008).…”

An over-12-Gbps on-chip transmission line interconnect with a pre-emphasis technique in 90 nm CMOS

“…Pre-emphasis techniques for compensating frequency dependences of loss are widely used for chip-to-chip high-speed communications [10], [11], and this paper introduces one to on-chip high-speed signal transmission. On-chip high-speed interconnects with passive equalization techniques have been proposed in the literature [8], [12], [13]. One of features of our interconnect is that transistors are used for performing equalization (preemphasis) at a transmitter (Tx) in order to save circuit area; reported passive equalization techniques for on-chip interconnects have applied capacitors or inductors that consume larger area than transistors.…”