An over-12-Gbps on-chip transmission line interconnect with a pre-emphasis technique in 90 nm CMOS

Abstract

This paper proposes an on-chip differential transmission line interconnect using a pre-emphasis technique for high-speed onchip signaling. The new transmitter with dynamic output-impedance control for pre-distortion of signals is presented. Simulation results showed that the proposed interconnect in 90 nm Si CMOS has possibilities of over-20-Gbps signaling and better energyper-bit performances than conventional on-chip high-speed interconnects. Our 5-mm-long interconnect can achieve 12.5 Gbps signaling with power consumption of 6.9 mW in measurements.

Enhancing effective throughput for transmission line-based bus

“…The key specs of our baseline bus are summarized in Table 1. While more detailed analyses of the link design and implementation could be helpful, they are beyond the scope of this paper and have been dealt with in some prior works [26,27,32,39] . We have also taped out a test chip (Figure 1) to further validate the circuit parameters obtained from our circuit simulations.…”

A design space exploration of transmission-line links for on-chip interconnect

“…Much work has been done investigating particular implementations of transmission line based on-chip interconnect and the supporting transceiver circuitry [22], [30]. These studies each present a particular design choice, as well as the circuit level ramifications of these choices.…”