A 20Gbps on-chip transceiver with equalization technique for global signal transmission

Mo, Wei; Chen, Keng; Liu, Yi; Wang, Qi

doi:10.1109/edssc.2012.6482834

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Signal Integrity Techniques1

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Cited by 5 publications

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“…To restore the signal shape at the output of the TCOIL, a tunable high-frequency correction circuits (continuous-time linear equalizers [9], EQ1 and EQ2 in figure 2(a)) were used in the design. Equalizers amplify the signal in the mid-frequency range.…”

Section: Signal Integrity Techniquesmentioning

confidence: 99%

2.56 Gbps CML transceiver for data concentrator ASIC

Serazetdinov¹

2022

J. Inst.

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2.56 Gbps CMOS CML-transceiver is presented. The key feature of the design is capability of working with specific inductive load and transmitting data to the remote room about 1 meter away from the experimentation vicinity. Some radiation tolerance techniques used are shown. Testing methodology is briefly described, and concepts in test board realization are provided. The transceiver was designed as an interface part of the data concentrator ASIC, intended for the frontend electronics of the time-projection chamber of the MPD experiment at NICA nuclotron.

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Section: Signal Integrity Techniquesmentioning

confidence: 99%