Highly Energy-Efficient On-Chip Pulsed-Current-Mode Transmission Line Interconnect

Maekawa, T.; Amakawa, Shuhei; Ito, Hiroyuki; Ishihara, Noboru; Masu, Kazuya

doi:10.5772/6884

Cited by 4 publications

(4 citation statements)

References 16 publications

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“…Author in [30] has proposed pulsed current mode signaling, in which generates return-to-zero (RZ) codes and does not consume static power achieves near speed of light latency and low bit energy through low swing current mode operation. And this signal modulates the transmitter energy to higher frequencies, where the effect of wire inductance can be minimized.…”

Section: F Using Pulsed Current Mode Signalingmentioning

confidence: 99%

A Survey Addressing on High Performance On-Chip VLSI Interconnect

Yousuff¹,

Hasan²,

Galib³

2013

International Journal of Electronics and Telecommunications

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Abstract-With the rapid increase in transmission speeds of communication systems, the demand for very high-speed lowpower VLSI circuits is on the rise. Although the performance of CMOS technologies improves notably with scaling, conventional CMOS circuits cannot simultaneously satisfy the speed and power requirements of these applications. In this paper we survey the state of the art of on-chip interconnect techniques for improving performance, power and delay optimization and also comparative analysis of various techniques for high speed design have been discussed.

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Section: F Using Pulsed Current Mode Signalingmentioning

confidence: 99%

A Survey Addressing on High Performance On-Chip VLSI Interconnect

Yousuff¹,

Hasan²,

Galib³

2013

International Journal of Electronics and Telecommunications

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“…The differential characteristic impedance of the line was around 100Ω. So far, various kind circuits has been developed using 0.35µm, 0.18µm and 90nm CMOS process: the orthodox CML (Current Mode Logic) [10,11], LVDS(Low voltage differential signaling) [12][13][14][15][16], PTLI(Pulsed-current Transmission Line) circuits [17,18], etc. Fig.…”

Section: Technology Evolution For Silicon Nano-electronicsmentioning

confidence: 99%

“…Our transmission line has small energy-per-bit performance, but the relatively larger area is required than the conventional RC interconnect. An FoM (Figure of Merit) can be introduced [18]; the FoM area is defined as (…”

Section: Technology Evolution For Silicon Nano-electronicsmentioning

confidence: 99%

See 1 more Smart Citation

Interconnect Design Challenges in Nano CMOS Circuit

Masu

Amakawa

Ito

et al. 2011

KEM

Self Cite

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In the conventional scaling scheme, interconnect delay cannot be reduced and the global interconnect delay become worse if the length of the wire is not scaled. The conventional approaches of global interconnect design are (1)introduction of inverse scaling concept where the upper metal layers have larger cross sections than lower metal layers, (2)insertion of repeaters, and (3) architecture level approach of multi/many core. In order to improve global interconnect delay even in aggressively miniaturized circuit, we have developed the transmission lien interconnect. This paper describes the novel analytical interconnect length distribution and discussion on future interconnect design direction. Then, recent our developments of the transmission line interconnect are described and performance comparison with another global wiring scheme such as optical interconnection is discussed.

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Estimation of bandwidth, voltage swing and DC coefficients for VLSI interconnects: current mode technique

Jadav

2024

International Journal of Electronics Letters

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Highly Energy-Efficient On-Chip Pulsed-Current-Mode Transmission Line Interconnect

Cited by 4 publications

References 16 publications

A Survey Addressing on High Performance On-Chip VLSI Interconnect

A Survey Addressing on High Performance On-Chip VLSI Interconnect

Interconnect Design Challenges in Nano CMOS Circuit

Estimation of bandwidth, voltage swing and DC coefficients for VLSI interconnects: current mode technique

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