A 16Gb/s 1^st-Tap FFE and 3-Tap DFE in 90nm CMOS

Abstract

Much effort has been made toward producing a high-speed multi-tap decision feedback equalizer (DFE), which would be a key component in removing intersymbol interference (ISI) in high-speed chip-to-chip communication. A loopunrolled approach is widely used in work toward the design of high-speed multitap DFEs. It eliminates the feedback operation in first post-cursor equalization [1][2][3], an operation that limits operational speed in conventional multi-tap DFEs. There are two problems, however, to its application to equalization of 16Gb/s signals. The first is that additional components in the feedback path, used for speculation on the basis of sampled data, increase 2 nd -tap feedback delay, preventing high-speed operations. The second problem is that jitter increase in equalized waveforms prevents accurate clock timing recovery because the 1 st tap ISI of the waveform is left un-equalized. In response to this situation, we have developed three techniques for achieving 16Gb/s communication: (1) an analog feedforward technique for high-speed 1 st -tap ISI equalization, (2) an analog feedforward technique for jitter reduction in equalized edges, and (3) technique for employing bypass feedback and a voltage swing limiter in order to speed-up both 2 ndtap and 3 rd -tap equalization. We have applied these techniques to a 16Gb/s equalizer fabricated in a 90nm CMOS process, and their use helps achieve a 33% increase in operating speed over that with conventional multi-tap DFEs [3].

A 12.5 Gb/s 6.6 mW receiver with analog equalizer and 1-tap DFE

“…Table 2 provides a comparison between this work and some recent published work. Compared to those designs that use only DFE as the equalizer in the receiver, such as [1,10,[13][14][15], the designed DFE in this work consumes a low amount of power. Note that in the proposed DFE, using a slicer with rail-to-rail output resulted in utilization of simple digital MUX circuits that in turn resulted in a relatively lower power consumption (considering the data rate, channel loss, and eye opening).…”

“…Satisfying such a timing constraint is a difficult task in high speed systems. To mitigate this problem, several techniques have been reported in the literature including loop-unrolling (speculation) [7], soft decision [8], half-rate and quarter-rate architectures [8,9], and canceling the first post-cursor ISI tap in transmitter using FFE [10]. In loop-unrolling technique, instead of detecting the previous bits and then subtracting their ISI effect from the recent bit, first, the ISI effects of the previous bits for all possible scenarios are subtracted from the recent bit in parallel, and then one of the cases is selected based on the previous detected bits using a MUX [7].…”

Data and edge decision feedback equalizer with >1.0-UI timing margin for both data and edge samples

“…If the ISI of edge sample is to be compensated independently, however, the feedback path has to be settled in less than 0.5-UI even with the speculative architecture. The first post-cursor ISI may be cancelled by feedforward equalization and thereby the timing burden is greatly reduced [9]. The feedforward path, however, was realized by a sample-and-hold (S/H) circuit which may generate feedthrough noise.…”

Differential Time Signaling Data-Link Architecture

“…In addition, the transmission channel is one of the limitations to increasing the link data rate due to the channel attenuation and reflections. Pre-emphases circuits at the transmitter side such as presented in [2][3][4] and equalization circuits [5,6] at the receiver side are used to compensate the channel attenuation and reflection to reduce the ISI effect.…”