Differential Time Signaling Data-Link Architecture

Abstract

A new time-based high-speed data-link architecture, which we call Differential time Signaling (DTS) is presented. A clock pulse is embedded in the transmitted signal and is used as a time reference against which the rising and falling data pulse edge timings are compared. Using the DTS approach, data encoding is achieved by spacing the time between the embedded clock edges and the data pulse edges using a hierarchical time-delay resolution assignment to each bit in the data sequence. The proposed link is shown to concentrate the signal energy in a low bandwidth while reducing clock jitter effect. A simulated 3 Gb/s 90 nm CMOS DTS link using a 500 MHz clock signal is also described to provide a flavor for a monolithic realization. As a proof of concept, 700 Mb/s and 1.6 Gb/s DTS-based links have been designed using a commercial FPGA board. The measured eye diagrams for the transmitted and received signals over a 40-inch FR4 channel are presented.

A Dual Modulation Pulse Position Modulation Approach in 130nm Cmos Technology for Time Based Serial Communication Links

“…Given the obliged limitations of CMOS technology scaling on the PAM and PWM, a time-based PPM-TDC architecture was presented in [8][9][10][11][12] and is shown in Fig.2. The authors displayed a low power time-based serial link employing a PPM modulation technique.…”

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“…PWM that utilizes the orthogonal characteristics of Walsh codes was also used in serial links to transmit multiple Walsh-code encoded data symbols via the same channel simultaneously [32]. Pulse-width-amplitude modulation (PWAM) that utilizes the advantages of both PAM and PWM simultaneously to further improve data rates by modulating data symbols both spatially and temporally becomes attractive [28, [33][34][35][36][37][38]. For example, 4PAM and 4PWM transmit 2 bits per symbol while 4PWAM transmits 4 bitsper symbol.…”

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