Abstract -Thermo-sensitive electrical parameter (TSEP) approaches are widely employed in the junction temperature extraction and prediction of power semiconductor devices. In this paper, the turn-off delay time is explored as an indicator of a TSEP to extract the junction temperature from high power insulated gate bipolar transistor (IGBT) modules. The parasitic inductor L eE between the Kelvin and power emitter terminals of an IGBT module is utilized to extract the turn-off delay time. Furthermore, the monotonic dependence between the junction temperature and turn-off delay time is investigated. The beginning and end point of the turn-off delay time can be determined by monitoring the induced voltage v eE across the inductor L eE . A dynamic switching characteristic test platform for high power IGBT modules is used to experimentally verify the theoretical analysis. The experimental results show that the dependency between IGBT junction temperature and turn-off delay time is near linear. It is established that the turn-off delay time is a viable TSEP with good linearity, fixed sensitivity and offers non-destruction on-line IGBT junction temperature extraction.Index Terms -Thermo-sensitive electrical parameter, high power IGBTs, on-line junction temperature extraction, turn-off delay time. I.0885-8993 (c) . His research interests include high power devices, advanced power converters and operation optimization for renewable energy based power systems. Dr. Li has published more than 100 peer-reviewed technical papers and holds over 30 issued/pending patents.Due to his excellent teaching and research contributions, Dr.
Users may download and print one copy of any publication from the public portal for the purpose of private study or research. You may not further distribute the material or use it for any profit-making activity or commercial gain. You may freely distribute the URL identifying the publication in the public portal.
The transformerless inverters with leakage current suppression have become an urgent application tendency in gridconnected photovoltaic systems because of low cost and high efficiency concerns. In this study, the half-bridge module and neutral point clamping (NPC) module are combined to derive an advanced hybrid-bridge transformerless inverter, which not only suppresses leakage current, but also reduces the required bus voltage compared to the conventional half-bridge or NPC inverters. A sinusoidal pulse-width modulation strategy without dead time is presented to enhance both the grid-connected power quality and system reliability. Furthermore, a detailed circuit performance comparison and practical evaluation are presented to show the clear advantages of the hybrid-bridge transformerless inverter. It also provides practical solutions for the leakage current minimisation by considering the contributing factors such as circuit parasitic parameters. Finally, a 3 kW prototype is tested to verify the theoretical analysis and main contributions of the study. 2 Existing topologies with leakage current suppression In transformerless PV grid-connected systems, the leakage current is the common-mode current which flows through www.ietdl.org
This paper proposes the adoption of the inherent emitter stray inductance LeE in high-power insulated gate bipolar transistor (IGBT) modules as a new dynamic thermo-sensitive electrical parameter (d-TSEP). Furthermore, a family of 14 derived dynamic TSEP candidates has been extracted and classified in voltage-based, time-based and charge-based TSEPs. Accordingly, the perspectives and the implementation challenges of the proposed method are discussed and summarized. Finally, high-power test platforms are designed and adopted to experimentally verify the theoretical analysis. Index Terms-High-power IGBT modules, auxiliary parasitic inductance, dynamic thermo-sensitive electrical parameters, junction temperature extraction principles. I. INTRODUCTION HE fast-growing pace of high-power conversion systems keep developing high-power Insulated Gate Bipolar Transistors (IGBTs) [1,2]. Thermal performance is currently regarded as one of the most important specifications in high-power modules, since both the short-term characteristics [3] and long-term ones are temperature-dependent [4,5]. In terms of the maximum operating junction temperature Tj, the commercially-available silicon-based power devices are rated up to 175 °C and the expected operation Tj in Wide-Band-Gap devices can reach 300 °C [6]. Hence, the knowledge of Tj has a crucial effect on the safe operation area of IGBTs. So far, many practical methods have been proposed [7-10]. Generally, the widely-studied Tj estimation methods in
IEEE Journal of Emerging and Selected Topics in Power Electronics Abstract -In silicon carbide (SiC) power MOSFETs, threshold voltage instability under high-temperature conditions has potential reliability threats to long-term operation. In this paper, the threshold voltage shifts caused by the instability mechanisms in accelerated power cycling tests for SiC MOSFETs are investigated. In conventional power cycling tests, the positive threshold voltage shift can cause successive on-state resistance increases, which can sequentially increase junction temperature variations gradually under fixed test conditions. In order to distinguish the increased die voltage drop from the bond wire resistance degradation, an independent measurement method is used during the power cycling tests. As the number of cycle increases, SiC die degradation can be observed independently of bond wire increases during the tests. It is studied that the SiC die degradation is associated with the threshold voltage instability mechanisms. Unlike the bond wire lift-off failure, the die degradation and the related die resistance increase can stop the power cycling test in earlier than expected. Additionally, a new test protocol considering die degradation is proposed for power cycling test. By means of power device analyzer, the failure mechanism and degradation performance of SiC MOSFETs before and after the power cycling test are compared and discussed. Finally, experimental results confirm the role of threshold voltage shifting and identify different failure mechanisms.
Abstract:In fast switching power semiconductors, the use of a fourth terminal to provide the reference potential for the gate signal-known as a kelvin-source terminal-is becoming common. The introduction of this terminal presents opportunities for condition monitoring systems. This article demonstrates how the voltage between the kelvin-source and power-source can be used to specifically monitor bond-wire degradation. Meanwhile, the drain to kelvin-source voltage can be monitored to track defects in the semiconductor die or gate driver. Through an accelerated aging test on 20 A Silicon Carbide Metal-Oxide-Semiconductor-Field-Effect Transistors (MOSFETs), it is shown that there are opposing trends in the evolution of the on-state resistances of both the bond-wires and the MOSFET die. In summary, after 50,000 temperature cycles, the resistance of the bond-wires increased by up to 2 mΩ, while the on-state resistance of the MOSFET dies decreased by approximately 1 mΩ. The conventional failure precursor (monitoring a single forward voltage) cannot distinguish between semiconductor die or bond-wire degradation. Therefore, the ability to monitor both these parameters due to the presence of an auxiliary-source terminal can provide more detailed information regarding the aging process of a device.
This study introduces the development advances and trend of power semiconductors used in hybrid and electric vehicles (HEV/EV). The status and forecast of power electronics' requirement in HEV/EV are discussed along with a review of the automotive standard of power semiconductor devices. The advances in automotive semiconductor technologies such as Sibased insulated-gate bipolar transistor (IGBT) and freewheeling diode (FRD) and SiC-based metal oxide semiconductor fieldeffect transistor (MOSFET) and Schottky barrier diode are presented. The advances in automotive semiconductor packaging technologies are illustrated from three considerations, which are the low inductance in high-power density packaging, lower thermal resistance designing, and advanced packaging technologies. The challenges and development trend of more reliable power semiconductors for HEV/EV are discussed. The challenges in Si devices are focused on power density, efficiency, reliability, and packages, while the high temperature and low inductances are the main challenges for SiC devices. Lastly, the development trend is discussed in terms of four aspects, the new generation Si IGBT for HEV/EV, such as recessed-emittertrench, reverse-conduction-IGBT, and smart IGBT; next generation SiC MOSFET; new packaging technology and material, such as planar packaging.
scite is a Brooklyn-based organization that helps researchers better discover and understand research articles through Smart Citations–citations that display the context of the citation and describe whether the article provides supporting or contrasting evidence. scite is used by students and researchers from around the world and is funded in part by the National Science Foundation and the National Institute on Drug Abuse of the National Institutes of Health.
hi@scite.ai
10624 S. Eastern Ave., Ste. A-614
Henderson, NV 89052, USA
Copyright © 2024 scite LLC. All rights reserved.
Made with 💙 for researchers
Part of the Research Solutions Family.