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Although data forwarding algorithms and protocols have been among the first set of issues explored in sensor networking, how to reliably deliver sensing data through a vast field of small, vulnerable sensors remains a research challenge. In this paper we present GRAdient Broadcast (GRAB), a new set of mechanisms and protocols which is designed specifically for robust data delivery in face of unreliable nodes and fallible wireless links. Similar to previous work [12,13], GRAB builds and maintains a cost field, providing each sensor the direction to forward sensing data. Different from all the previous approaches, however, GRAB forwards data along a band of interleaved mesh from each source to the receiver. GRAB controls the width of the band by the amount of credit carried in each data message, allowing the sender to adjust the robustness of data delivery. GRAB design harnesses the advantage of large scale and relies on the collective efforts of multiple nodes to deliver data, without dependency on any individual ones. We have evaluated the GRAB performance through both analysis and extensive simulation. Our analysis shows quantitatively the advantage of interleaved mesh over multiple parallel paths. Our simulation further confirms the analysis results and shows that GRAB can successfully deliver over 90% of packets with relatively low energy cost, even under the adverse conditions of 30% node failures compounded with 15% link message losses.

This brief presents an efficient and configurable multiple-input-multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 × 2/3 × 3/4 × 4 MIMO and quadratic phase-shift keying/16-state quadratic amplitude modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability. To further improve the IC implementation efficiency, this detector also uses a candidate-sharing structure for partial Euclidean distance calculation and a two-stage sorter for survivor node selection. A test chip has been fabricated using 0.13-µm single-poly-and eight-metal (1P8M) CMOS technology with a core area of 3.9 mm 2 . Operating at 1.2-V supply with 137.5-MHz clock, the chip achieves 1.1-Gb/s throughput and consumes 115 pJ per bit, representing 40% more energy efficient than state of the art in the open literature.Index Terms-Detector, early-pruned K-Best, multiple-inputmultiple-output (MIMO), very large scale integration (VLSI).

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Abstract：A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the fft processor. I. IntroductionUltra Wide band (UWB) is en emerging technology that offers great promises to satisfy the growing demand for low cost and high speed digital wireless home network. The OFDM based UWB communication system is supposed to process and transfer data at 528Mbps[1][2], which poses a challenge to realize the application of UWB system. FFT processor is one of the core modules with high computational complexity in the UWB system. How to improve the signal processing capability and to reduce the power consumption as well as the hardware cost of a FFT processor have now all become challenging targets. What's more, in 2*2 MIMO-OFDM system, which have been shown to be an efficient approach to make benefits of spatial and frequency diversities[3], the FFT processor is demanded to deal with two parallel 64-points operations. Fig. 1 and Fig. 2 respectively show the structure of SISO and MIMO UWB system. Several FFT processors have been realized different algorithms and structure in the last decade, such as [4] the processor with multi-path delay commutator (MDC) structure. It features high data transmission rate but high hardware cost.[5] has improved the MDC structure to a mixed radix multi-path delay feedback(MRMDF) structure for the 128-points FFT processor in order to decrease the hardware cost. But the MRMDF structure has a difficulty in meeting the requirement of transmission rate and the

Mainstream indoor localization technologies rely on RF signatures that require extensive human efforts to measure and periodically re-calibrate signatures. The progress to ubiquitous localization remains slow. In this study, we explore Sextant, an alternative approach that leverages environmental reference objects such as store logos. A user uses a smartphone to obtain relative position measurements to such static reference objects for the system to triangulate the user location. Sextant leverages image matching algorithms to automatically identify the chosen reference objects by photo-taking, and we propose two methods to systematically address image matching mistakes that cause large localization errors. We formulate the benchmark image selection problem, prove its NP-completeness, and propose a heuristic algorithm to solve it. We also propose a couple of geographical constraints to further infer unknown reference objects. To enable fast deployment, we propose a lightweight site survey method for service providers to quickly estimate the coordinates of reference objects. Extensive experiments have shown that Sextant prototype achieves 2 − 5m accuracy at 80-percentile, comparable to the industry state-of-the-art, while covering a 150 × 75m mall and 300 × 200m train station requires a one time investment of only 2 − 3 man-hours from service providers.

Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.

High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.