Atomic layer deposition (ALD) processes are reported for ruthenium (Ru) and ruthenium oxide (RuO 2 ) using a zero-oxidation state liquid precursor, η 4 -2,3-dimethylbutadiene ruthenium tricarbonyl [Ru(DMBD)(CO) 3 ]. Both ALD Ru and RuO 2 films were deposited using alternating N 2 -purge-separated pulses of Ru(DMBD)(CO) 3 and O 2 . ALD Ru metal films were deposited via short (2 s) pulses of O 2 . Ru films have an ALD temperature window from 290 to 320 °C with a GPC of 0.067 nm/ cycle and a negligible nucleation delay on SiO 2 . Ru films show a strong hexagonal crystal structure with low resistivity of approximately 14 μΩ cm at 320 °C. RuO 2 films were deposited using longer (20 s) pulses of either molecular O 2 or O 2 plasma. RuO 2 films deposited via thermal ALD using molecular O 2 have a temperature window from 220 to 240 °C with a GPC and nucleation delay on SiO 2 of 0.065 nm/cycle and 35 cycles, respectively. Thermal ALD RuO 2 films show a distinct rutile phase microstructure with a resistivity of approximately 62 μΩ cm. In comparison to thermal ALD, the PEALD RuO x films show a lower growth rate and higher nucleation delay of 0.029 nm/cycle and 76 cycles, respectively. PEALD RuO x films also exhibit less distinct crystallinity and a higher resistivity of 377 μΩ cm.

High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

The energy barrier heights between an ultra-smooth amorphous metal electrode, ZrCuAlNi, and several atomic layer deposited (ALD) insulators are measured using internal photoemission (IPE) spectroscopy. ZrCuAlNiinsulator barriers are characterized within metal-insulator-metal (MIM) stacks with Al top contacts and results are compared with the Al/insulator barrier heights. The measured barrier heights at the ZrCuAlNi interface are found to be 3.3, 3.2, 3.0, and 2.2 eV for SiO 2 , Al 2 O 3 , HfO 2 , and ZrO 2 , respectively. This barrier height trend is consistent with the electron affinity of the respective oxides. However, barriers for SiO 2 and Al 2 O 3 are smaller than that ideally expected based on the reported vacuum work function of ZrCuAlNi, indicating a smaller ZrCuAlNi effective work function in these device structures. The measured Al barrier height results confirm previous reports of a negative dipole at the Al-ALD insulator interface.

Bismuth oxide thin films were deposited by atomic layer deposition using Bi(OCMe2iPr)3 and H2O at deposition temperatures between 90 and 270 °C on Si3N4, TaN, and TiN substrates. Films were analyzed using spectroscopic ellipsometry, x-ray diffraction, x-ray reflectivity, high-resolution transmission electron microscopy, and Rutherford backscattering spectrometry. Bi2O3 films deposited at 150 °C have a linear growth per cycle of 0.039 nm/cycle, density of 8.3 g/cm3, band gap of approximately 2.9 eV, low carbon content, and show the β phase structure with a (201) preferred crystal orientation. Deposition temperatures above 210 °C and postdeposition anneals caused uneven volumetric expansion, resulting in a decrease in film density, increased interfacial roughness, and degraded optical properties.

Metal-insulator-insulator-metal (MIIM) capacitors with bilayers of Al 2 O 3 and SiO 2 are deposited at 200°C via plasma enhanced atomic layer deposition. Employing the cancelling effect between the positive quadratic voltage coefficient of capacitance (αVCC) of Al 2 O 3 and the negative αVCC of SiO 2 , devices are made that simultaneously meet the International Technology Roadmap for Semiconductors 2020 projections for capacitance density, leakage current density, and voltage nonlinearity. Optimized bilayer Al 2 O 3 /SiO 2 MIIM capacitors exhibit a capacitance density of 10.1 fF/μm 2 , a leakage current density of 6.8 nA/cm 2 at 1 V, and a minimized αVCC of −20 ppm/V 2 . Index Terms-Al 2 O 3 /SiO 2 , metal-insulator-metal capacitors, MIMCAPs, MIIM, plasma enhanced atomic layer deposition, PEALD, quadratic voltage coefficient of capacitance, αVCC.

Metals with low enthalpy of oxide formation (ΔHox) are used to examine the influence of the metal/dielectric interface, in the absence of a significant interfacial layer oxide (ILO), on the voltage nonlinearity of capacitance for metal-insulator-metal capacitors. For both atomic layer deposited Al2O3 and HfO2 dielectrics, Ag electrode devices show the lowest quadratic electric field coefficient of capacitance (αECC), followed in increasing order by Au, Pd, and Ni. The difference between the metals is greater for thinner dielectrics, which is consistent with increased influence of the interface. In addition, with decreasing dielectric thickness the quadratic voltage field coefficient of capacitance increases, whereas αECC decreases. It is proposed that the thickness dependencies are due to an interaction between vertical compression of the dielectric under an applied bias and the concomitant lateral expansion induced stress that is concentrated near the interface. Through this interaction, the metal interface inhibits lateral expansion of the dielectric resulting in a reduced αECC. Indeed, αECC is found to increase with the increasing lattice mismatch at the metal/dielectric interface, likely due to edge dislocations. Finally, Al, a high ΔHox metal, is found to fit the trend for Al2O3 but not for HfO2, due to the formation of a thin reduced-k ILO at the HfO2/Al interface. These results suggest that minimization of metal/dielectric lattice mismatch may be a route to ultra-low nonlinearity in highly scaled metal-insulator-metal devices.

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