Review—Beyond the Highs and Lows: A Perspective on the Future of Dielectrics Research for Nanoelectronic Devices

Abstract

High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past two decades, but they have recently reached a state of maturity and perhaps the limits of their scaling. Based on this, there is a need for a systematic review summarizing not only the historic research and achievements on high-k and low-k dielectrics, but also emerging device applications as well as an outlook of future challenges. We begin by first reviewing the factors that drove the emergence of low-k and high-k materials in nanoelectronics as ILD and gate dielectric materials, respectively, and the challenges and limits these materials ultimately approached in terms of permittivity scaling. We then illustrate that gate dielectric and ILD applications represent just a small fraction of the numerous dielectrics utilized in present day nanoelectronic products where permittivity scaling is now being increasingly demanded for materials such as dielectric spacers, trench isolation, and etch stopping layers. We conclude by examining the numerous new applications for dielectric materials that are emerging as the semiconductor industry transitions to novel patterning schemes, prepares for life post CMOS scaling, and explores ways to natively embed device functionality in the metal interconnect. For the former, we specifically examine the “colorful” requirements for the various enabling dielectric hardmask and spacer materials utilized in pitch division-multi-pattern processes and then discuss the role that selective area deposition of dielectrics and metals could play in reducing the complexity of such patterning processes. For the latter, we review the use of both high-k and low-k dielectrics in various metal-insulator-metal (MIM) structures as Fermi level de-pinning layers, tunnel diodes, and back-end-of-line (BEOL) compatible capacitive and resistive switching random access memory (ReRAM) elements. We further examine how dielectrics can hinder or aid new forms of computing such as quantum and neuromorphic in reaching their full potential. In conclusion, we find that while the field of dielectrics has a long history, it remains vibrant with numerous exciting new and old research vectors awaiting further exploration.

Area-Selective Atomic Layer Deposition of TiN Using Aromatic Inhibitor Molecules for Metal/Dielectric Selectivity

“…Nitrides play an important role in the semiconductor industry with applications such as diffusion barriers, , spacers, , adhesion layers, , etch masks, , and work function metals. , However, the number of developed processes for area-selective ALD of nitrides is very limited. ,, Nitrides are typically deposited using plasma-assisted ALD processes in case low temperature processing is required . Because most area-selective ALD approaches are not compatible with either plasmas or high substrate temperatures, area-selective ALD of nitrides is considered to be very challenging.…”

“…10−13 Because these SAMs are typically applied before the start of the ALD process, thermal degradation of the SAM or reactions between the SAM and the ALD reactants during the process often limit the selectivity. 11,14,15 Nitrides play an important role in the semiconductor industry with applications such as diffusion barriers, 16,17 spacers, 16,18 adhesion layers, 19,20 etch masks, 16,21 and work function metals. 22,23 However, the number of developed processes for area-selective ALD of nitrides is very limited.…”

Compact Modeling Technology for the Simulation of Integrated Circuits Based on Graphene Field‐Effect Transistors

“…[26] Graphene channels and their associated interfaces have been optimized towards a significant reduction of traps and defects in transistor architectures e.g., through passivation [27,28] and/or encapsulation techniques. [29,30] However, gate oxide has been a major issue in graphene transistors as well as in other emerging [26] and mature [31] FET technologies owing to scalability limitations; [26] thus, deep oxide (border) traps still affect the device performance. [32][33][34][35] High-κ insulators, such as HfO2 and Al2O3, as well as layered 2D insulators, such as hexagonal boron nitride (hBN), have been used to fabricate high-performance GFETs.…”

Role of Cyclopentadienyl Ligands of Group 4 Precursors toward High-Temperature Atomic Layer Deposition

“…High-k materials such as TiO 2 , ZrO 2 , and HfO 2 have attracted considerable attention for application in fabrication electronic devices such as a complementary metal oxide semiconductor (CMOS) and dynamic random access memory (DRAM). − Atomic layer deposition (ALD) is one of the most important technologies for depositing high-k material thin films, due to the conformality and thickness control at the atomic level. − It has been suggested that the ALD process at high temperatures above 300 °C may enhance the material properties of the high-k material thin films such as density, impurity level, and crystallinity. These advantages of high-temperature ALD can be present only if suitable metal precursors that can withstand high temperatures are available.…”