The trap-induced hysteresis on the performance of a graphene field-effect transistor is experimentally diminished here by applying consecutive gate-to-source voltage pulses of opposing polarity. This measurement scheme is a practical and suitable approach to obtain reproducible device characteristics. Trap-affected and trap-reduced experimental data enable a discussion regarding the impact of traps on static and dynamic device performance. An analytical drain current model calibrated with the experimental data enables the study of the traps effects on the channel potential within the device. High-frequency figures of merit and the intrinsic gain of the device obtained from both experimental and synthetic data with and without hysteresis show the importance of considering the generally overlooked impact of traps for analog and high-frequency applications.

Channel length scaling in graphene field effect transistors (GFETs) is key in the pursuit of higher performance in radio frequency electronics for both rigid and flexible substrates. Although two-dimensional (2D) materials provide a superior immunity to Short Channel Effects (SCEs) than bulk materials, they could dominate in scaled GFETs. In this work, we have developed a model that calculates electron and hole transport along the graphene channel in a drift-diffusion basis, while considering the 2D electrostatics. Our model obtains the self-consistent solution of the 2D Poisson's equation coupled to the current continuity equation, the latter embedding an appropriate model for drift velocity saturation. We have studied the role played by the electrostatics and the velocity saturation in GFETs with short channel lengths . Severe scaling results in a high degradation of GFET output conductance. The extrinsic cutoff frequency follows a 1⁄ scaling trend, where the index fulfills ≤ 2. The case = 2 corresponds to long-channel GFETs with low source/drain series resistance, that is, devices where the channel resistance is controlling the drain current.For high series resistance, decreases down to = 1, and it degrades to values of < 1 because of the SCEs, especially at high drain bias. The model predicts high maximum oscillation frequencies above 1 THz for channel lengths below 100 nm, but, in order to obtain these frequencies, it is very important to minimize the gate series resistance. The model shows very good agreement with experimental current voltage curves obtained from short channel GFETs and also reproduces negative differential resistance, which is due to a reduction of diffusion current.The RF FoMs strongly depend on the particular values of and . A lower value of will result in a lowering of , while a higher value of will lower max . Short channels and/or high biases can make and strongly deviate from the long channel prediction, even if the 2D character of graphene provides a superior control over the charge in the channel when compared to bulk materials. This is due to the fact that SCEs degrade the ability of the gate to control electrostatically the carrier concentration in the channel. In

In this study, we report the progress made towards the definition of a modular compact modeling technology for graphene field-effect transistors (GFET) that enables the electrical analysis of arbitrary GFET-based integrated circuits. A set of primary models embracing the main physical principles defines the ideal GFET response under DC, transient (time domain), AC (frequency domain), and noise (frequency domain) analysis. Other set of secondary models accounts for the GFET non-idealities, such as extrinsic-, short-channel-, trapping/detrapping-, self-heating-, and non-quasi static-effects, which could have a significant impact under static and/or dynamic operation. At both device and circuit levels, significant consistency is demonstrated between the simulation output and experimental data for relevant operating conditions. Additionally, we provide a perspective of the challenges during the scale up of the GFET modeling technology towards higher technology readiness levels while drawing a collaborative scenario among fabrication technology groups, modeling groups, and circuit designers.Received: ((will be filled in by the editorial staff))Revised: ((will be filled in by the editorial staff))

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The Dirac voltage of a graphene field-effect transistor (GFET) stands for the gate bias that sets the charge neutrality condition in the channel, thus resulting in a minimum conductivity. Controlling its dependence on the terminal biases is crucial for the design and optimization of radio-frequency applications based on multiple GFETs. However, the previous analysis of such dependence carried out for single devices is uncomplete and if not properly understood could result in circuit designs with poor performance. The control of the Dirac point shift (DPS) is particularly important for the deployment of graphene-based differential circuit topologies where keeping a strict symmetry between the electrically balanced branches is essential for exploiting the advantages of such topologies. This note sheds light on the impact of terminal biases on the DPS in a real device and sets a rigorous methodology to control it so to eventually optimize and exploit the performance of radio-frequency applications based on GFETs.