Design of Low-Power, 1GS/s Throughput FFT Processor for MIMO-OFDM UWB Communication System

Abstract

Abstract：A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the fft processor. I. IntroductionUltra Wide band (UWB) is en emerging technology that offers great promises to satisfy the growing demand for low cost and high speed digital wireless home network. The OFDM based UWB communication system is supposed to process and transfer data at 528Mbps[1][2], which poses a challenge to realize the application of UWB system. FFT processor is one of the core modules with high computational complexity in the UWB system. How to improve the signal processing capability and to reduce the power consumption as well as the hardware cost of a FFT processor have now all become challenging targets. What's more, in 2*2 MIMO-OFDM system, which have been shown to be an efficient approach to make benefits of spatial and frequency diversities[3], the FFT processor is demanded to deal with two parallel 64-points operations. Fig. 1 and Fig. 2 respectively show the structure of SISO and MIMO UWB system. Several FFT processors have been realized different algorithms and structure in the last decade, such as [4] the processor with multi-path delay commutator (MDC) structure. It features high data transmission rate but high hardware cost.[5] has improved the MDC structure to a mixed radix multi-path delay feedback(MRMDF) structure for the 128-points FFT processor in order to decrease the hardware cost. But the MRMDF structure has a difficulty in meeting the requirement of transmission rate and the

Fast Fourier Transform Processors: Implementing FFT and IFFT Cores for OFDM Communication Systems

“…(Cortés et al, 2007;He & Torkelson, 1998;Lee & Park, 2007;Lee et al, 2006;Turrillas et al, 2010;Wang et al, 2005) propose Single-Path Delay Feedback (SDF) architectures. (Lin et al, 2005;Liu et al, 2007) employ an Multi-Path Delay Feedback (MDF) architecture. (Bidet et al, 1995) proposes a Single-Path Delay Commutator (SDC) architecture and (Jung et al, 2005;Saberinia, 2006) chose an Multi-Path Delay Commutator (MDC) architecture.…”

“…(Jung et al, 2005) 64 Pipeline-MDC r-2 DIT WLAN (Maharatna et al, 2004) 64 Pipeline r-2 DIT WLAN (Serrá et al, 2004) 64 Monoprocessor r-2 DIT WLAN (Lin et al, 2005) 128 Pipeline-MRMDF MR 2/2 3 DIF UWB (Saberinia, 2006) 128 Pipeline-BRMDC r-2 DIF UWB (Lee et al, 2006) 128 Pipeline-SDF r-2 4 DIF UWB (Liu et al, 2007) 64/128 Pipeline 8-path DF MR DIF UWB (Cortés et al, 2007) 128 Pipeline r-2 4 DIF UWB (Bidet et al, 1995) 8192 Pipeline-SDC r-4/2 DIF DVB-T (Lin, Liu & Lee, 2004) 8192 Parallel r-2 3 DIT DVB-T (Wang et al, 2005) 2/8 K Pipeline-SDF r-4/2 DIF DVB-T ( Lenart & Owal, 2006) 2/4/8 K Pipeline-SDF r-2 2 DIF DVB-T/H (Lee & Park, 2007) 8K Pipeline-SDF BD DVB-T (He & Torkelson, 1998) 1024 Pipeline-SDF r-2 2 DIF OFDM (Kuo et al, 2003) 64-2048 Cached memory r-2 DIT OFDM (Chang & Park, 2004) 1024 Monoprocessor r-4 DIF OFDM (Jiang et al, 2004) 64 Parallel r-2 DIT OFDM (Lin, Lin, Chen & Chang, 2004) 64 Pipeline r-2 DIF MIMO (Rudagi et al, 2010) 64 Pipeline r-2 DIT OFDM (Yu et al, 2011) 64 Pipeline r-2 DIF OFDM (Tsai et al, 2011) 64 Pipeline MR OFDM (Turrillas et al, 2010) 32 K Pipeline r-2 k DIF DVB-T2 Table 1. FFT proposals for OFDM systems…”

“…• For the pipeline architectures, different FFT algorithms such as radix 2 (Jung et al, 2005;Rudagi et al, 2010;Saberinia, 2006;Yu et al, 2011), mixed radix (MR) (Bidet et al, 1995;Lin, Lin, Chen & Chang, 2004;Lin et al, 2005;Liu et al, 2007;Tsai et al, 2011;Wang et al, 2005), radix 2 2 (Cortés et al, 2007;He & Torkelson, 1998;Lenart & Owal, 2006;Turrillas et al, 2010), radix 2 3 (Cortés et al, 2007;He & Torkelson, 1998;Turrillas et al, 2010), radix 2 4 (Cortés et al, 2007;Lee et al, 2006;Turrillas et al, 2010) and balanced decomposition (BD) (Lee & Park, 2007) which reduces the number of twiddle factors have been proposed.…”

“…Thus, (Chang & Park, 2004;Cortés et al, 2007;He & Torkelson, 1998;Jiang et al, 2004;Jung et al, 2005;Kuo et al, 2003;Lee et al, 2006;Lin, Lin, Chen & Chang, 2004;Lin et al, 2005;Liu et al, 2007;Maharatna et al, 2004;Saberinia, 2006;Serrá et al, 2004) proposed fixed-point FFTs for N < 8192. Nevertheless, (Wang et al, 2005) also used the fixed-point format for large FFTs.…”

“…Examples of these representations can be found in (He & Torkelson, 1998;Lee & Park, 2007;Lee et al, 2006;Lin, Lin, Chen & Chang, 2004;Lin, Liu & Lee, 2004;Lin et al, 2005;Liu et al, 2007;Maharatna et al, 2004;Tsai et al, 2006). These representations do not help the designer to understand the algorithm fast, therefore, making it difficult to relate it to its HW resources.…”