This brief presents an efficient and configurable multiple-input-multiple-output (MIMO) signal detector design solution and its high-speed IC implementation. This detector can support 2 × 2/3 × 3/4 × 4 MIMO and quadratic phase-shift keying/16-state quadratic amplitude modulation (QAM)/64-state QAM modulation configurations. The detection algorithm employs an early-pruned technique that can reduce up to 46% node extensions in the K-Best sphere decoder while maintaining an almost maximum-likelihood performance. A parallel multistage folded very large scale integration architecture is accordingly developed that can achieve high detection throughput and configurability. To further improve the IC implementation efficiency, this detector also uses a candidate-sharing structure for partial Euclidean distance calculation and a two-stage sorter for survivor node selection. A test chip has been fabricated using 0.13-µm single-poly-and eight-metal (1P8M) CMOS technology with a core area of 3.9 mm 2 . Operating at 1.2-V supply with 137.5-MHz clock, the chip achieves 1.1-Gb/s throughput and consumes 115 pJ per bit, representing 40% more energy efficient than state of the art in the open literature.Index Terms-Detector, early-pruned K-Best, multiple-inputmultiple-output (MIMO), very large scale integration (VLSI).

Abstract-This paper presents for the first time the design, fabrication, and demonstration of micromachined silicon dielectric waveguide based sub-THz interconnect channel for high efficiency, low cost sub-THz interconnect, aiming to solve the longstanding intra-/inter-chip interconnect problem. Careful studies of the loss mechanisms in the proposed sub-THz interconnect channel are carried out to optimize the design. Both theoretical and experimental results are provided with good agreement. To guide the channel design, a new Figure-of-Merit is also defined. The insertion loss of this first prototype with a 6-mm long interconnect channel is about 8.4 dB at 209.7 GHz, with a 3-dB bandwidth of 12.6 GHz.

The rapid development of machine vision applications demands hardware that can sense and process visual information in a single monolithic unit to avoid redundant data transfer. Here, we design and demonstrate a monolithic vision enhancement chip with light-sensing, memory, digital-to-analog conversion, and processing functions by implementing a 619-pixel with 8582 transistors and physical dimensions of 10 mm by 10 mm based on a wafer-scale two-dimensional (2D) monolayer molybdenum disulfide (MoS 2 ). The light-sensing function with analog MoS 2 transistor circuits offers low noise and high photosensitivity. Furthermore, we adopt a MoS 2 analog processing circuit to dynamically adjust the photocurrent of individual imaging sensor, which yields a high dynamic light-sensing range greater than 90 decibels. The vision chip allows the applications for contrast enhancement and noise reduction of image processing. This large-scale monolithic chip based on 2D semiconductors shows multiple functions with light sensing, memory, and processing for artificial machine vision applications, exhibiting the potentials of 2D semiconductors for future electronics.

Abstract：A new 8PBF structure for 64/128 flexible point FFT processor is proposed. The processor, which is based on 8*8*2 mixed radix algorithm, can deal with multiple inputs more efficiently for MIMO applications. The 8PFB structure efficiently brings the throughput of the processor up to 1GS/s and the chances of register reverse down, reducing the power dissipation remarkably. Meanwhile the modified shift-add algorithm can remove complex multipliers in the fft processor. I. IntroductionUltra Wide band (UWB) is en emerging technology that offers great promises to satisfy the growing demand for low cost and high speed digital wireless home network. The OFDM based UWB communication system is supposed to process and transfer data at 528Mbps[1][2], which poses a challenge to realize the application of UWB system. FFT processor is one of the core modules with high computational complexity in the UWB system. How to improve the signal processing capability and to reduce the power consumption as well as the hardware cost of a FFT processor have now all become challenging targets. What's more, in 2*2 MIMO-OFDM system, which have been shown to be an efficient approach to make benefits of spatial and frequency diversities[3], the FFT processor is demanded to deal with two parallel 64-points operations. Fig. 1 and Fig. 2 respectively show the structure of SISO and MIMO UWB system. Several FFT processors have been realized different algorithms and structure in the last decade, such as [4] the processor with multi-path delay commutator (MDC) structure. It features high data transmission rate but high hardware cost.[5] has improved the MDC structure to a mixed radix multi-path delay feedback(MRMDF) structure for the 128-points FFT processor in order to decrease the hardware cost. But the MRMDF structure has a difficulty in meeting the requirement of transmission rate and the

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An on-chip metamaterial resonator is demonstrated in 65 nm CMOS at 80 GHz for millimetre-wave integrated circuit (MMIC) applications. The resonator is based on a differential metamaterial transmission-line (T-line) loaded with a split ring resonator (SRR), which can enhance the EM energy coupling and further improve the quality factor (Q). Measurement results indicate that the proposed differential SRR (DSRR) Tline shows a sharp stopband with maximum 35 dB rejection. Moreover, the metamaterial property of the DSRR T-line is validated from the measurement results. It is the first on-chip demonstration of a millimetre-wave metamaterial resonator in 65 nm CMOS, which can be integrated for a low-noise oscillator and high-Q filter design in a 100 GHz MMIC communication system.

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