Platform-Based Resource Binding Using a Distributed Register-File Microarchitecture

Abstract

Behavior synthesis and optimization beyond the register transfer level require an efficient utilization of the underlying platform features. This paper presents a platform-based resource-binding approach using a distributed register-file microarchitecture (DRFM) that makes efficient use of distributed embedded memory blocks as register files in modern FPGAs. A DRFM contains multiple islands, each having a local register file, a functional unit pool and data-routing logic. Compared with the traditional discrete-register counterpart, a DRFM allows use of the platform-featured on-chip memory or register-file IP blocks to implement its local register files, and this results in substantial saving of multiplexing logic and global interconnects. DRFM provides a useful architectural template and a direct optimization objective for minimizing interisland connections for synthesis algorithms. Based on DRFM, we propose a novel binding algorithm focusing on the minimization of the inter-island connections. By applying our approach, significant reductions on multiplexors and global-interconnections are observed. On the Xilinx Virtex II FPGA platform, our experimental results show a 2X logic area reduction and a 7.8% performance improvement, compared with the traditional discrete-register-based approach.

A generalized control-flow-aware pattern recognition algorithm for behavioral synthesis

“…Our work is compared to a traditional behavioral synthesis flow [6,7], and the DFG pattern-based synthesis result in [4]. Table II shows the QoR of our proposed pattern-based synthesis algorithm compared to the other two approaches.…”

“…Table II shows the QoR of our proposed pattern-based synthesis algorithm compared to the other two approaches. In Table II, the second, third and fifth columns are the synthesis results for the number of registers used without pattern-based technique [6,7], with a DFG pattern-based technique [4], and with CDFG pattern-based technique, respectively. Similarly, columns 7 to 11 list the amount and comparison of logic elements usage.…”

Pattern-based behavior synthesis for FPGA resource reduction

“…There is extensive literature on general binding algorithms in high-level synthesis like [31,18,22,8,11]. For example, the weighted bipartite matching approach [18] tries to minimize the multiplexers following a step-by-step method, and it is later enhanced by the co-family based approach in [8].…”

Towards layout-friendly high-level synthesis

“…Such metrics are usually derived from a graph representation of the netlist without performing layout. Widely used structural metrics include the total multiplexer inputs [7,22,23,29], the number of global interconnects [12,32], the total cut size [24], etc. These metrics are often easier to obtain and are more stable (i.e., not dependent on the layout algorithm), but their accuracy is often a concern.…”